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5d29050f58
The bug manifests when there are two loads and two stores chained as follows in a DAG, (ld v3f32) -> (st f32) -> (ld v3f32) -> (st f32) and the stores' values are extracted from the preceding vector loads. MergeConsecutiveStores would replace the first store in the chain with the merged vector store, which would create a cycle between the merged store node and the last load node that appears in the chain. This commits fixes the bug by replacing the last store in the chain instead. rdar://problem/20275084 Differential Revision: http://reviews.llvm.org/D8849 llvm-svn: 234430
53 lines
1.6 KiB
LLVM
53 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
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; CHECK: merge_stores_can
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; CHECK: callq foo
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; CHECK: xorps %xmm0, %xmm0
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; CHECK-NEXT: movups %xmm0
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; CHECK: callq foo
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; CHECK: ret
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declare i32 @foo([10 x i32]* )
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define i32 @merge_stores_can() nounwind ssp {
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%object1 = alloca [10 x i32]
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%ret0 = call i32 @foo([10 x i32]* %object1) nounwind
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%O1_1 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 1
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%O1_2 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 2
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%O1_3 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 3
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%O1_4 = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 4
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%ld_ptr = getelementptr [10 x i32], [10 x i32]* %object1, i64 0, i32 9
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store i32 0, i32* %O1_1
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store i32 0, i32* %O1_2
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%ret = load i32, i32* %ld_ptr ; <--- does not alias.
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store i32 0, i32* %O1_3
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store i32 0, i32* %O1_4
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%ret1 = call i32 @foo([10 x i32]* %object1) nounwind
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ret i32 %ret
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}
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; CHECK: merge_stores_cant
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; CHECK-NOT: xorps %xmm0, %xmm0
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; CHECK-NOT: movups %xmm0
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; CHECK: ret
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define i32 @merge_stores_cant([10 x i32]* %in0, [10 x i32]* %in1) nounwind ssp {
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%O1_1 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 1
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%O1_2 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 2
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%O1_3 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 3
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%O1_4 = getelementptr [10 x i32], [10 x i32]* %in1, i64 0, i32 4
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%ld_ptr = getelementptr [10 x i32], [10 x i32]* %in0, i64 0, i32 2
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store i32 0, i32* %O1_1
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store i32 0, i32* %O1_2
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%ret = load i32, i32* %ld_ptr ; <--- may alias
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store i32 0, i32* %O1_3
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store i32 0, i32* %O1_4
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ret i32 %ret
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}
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