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Momchil Velikov a94ebc7b81 [AArch64][SVE] Allow explicit size specifier for predicate operand
... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the exsting behaviour of not requiring an explicit size
specifier. The preferred disasembly is *with* the specifier.

This is implemented by redefining intruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Differential Revision: https://reviews.llvm.org/D65145

llvm-svn: 367019
2019-07-25 13:56:04 +00:00
2019-07-23 16:27:34 +00:00
2016-01-26 21:29:08 +00:00
2019-07-17 07:02:02 +00:00
2019-02-19 20:38:51 +00:00

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