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33e593fd71
If the literal is being folded into src0, it doesn't matter if it's an SGPR because it's being replaced with the literal. Also fixes initially selecting 32-bit versions of some instructions which also confused commuting. llvm-svn: 281117
15 lines
557 B
LLVM
15 lines
557 B
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}main:
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3f4353f8, v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0xbf4353f8, v{{[0-9]+}}
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define amdgpu_vs void @main(float) {
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main_body:
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%1 = fmul float %0, 0x3FE86A7F00000000
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%2 = fmul float %0, 0xBFE86A7F00000000
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %1, float %1, float %2, float %2)
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ret void
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}
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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