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https://github.com/RPCS3/llvm-mirror.git
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1686869897
ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit. This fix checks if the immediate version can be used under this constraints and if we can convert ADDS to SUBS or vice versa to support negative immediates. Also update the test cases to test the immediate versions. llvm-svn: 214470
600 lines
17 KiB
LLVM
600 lines
17 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
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; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
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;
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; Get the actual value of the overflow bit.
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;
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define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: saddo1.i32
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; CHECK: adds {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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; Test the immediate version.
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define zeroext i1 @saddo2.i32(i32 %v1, i32* %res) {
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entry:
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; CHECK-LABEL: saddo2.i32
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; CHECK: adds {{w[0-9]+}}, w0, #4
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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; Test negative immediates.
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define zeroext i1 @saddo3.i32(i32 %v1, i32* %res) {
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entry:
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; CHECK-LABEL: saddo3.i32
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; CHECK: subs {{w[0-9]+}}, w0, #4
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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; Test immediates that are too large to be encoded.
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define zeroext i1 @saddo4.i32(i32 %v1, i32* %res) {
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entry:
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; CHECK-LABEL: saddo4.i32
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; CHECK: adds {{w[0-9]+}}, w0, {{w[0-9]+}}
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: saddo1.i64
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; CHECK: adds {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
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entry:
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; CHECK-LABEL: saddo2.i64
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; CHECK: adds {{x[0-9]+}}, x0, #4
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
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entry:
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; CHECK-LABEL: saddo3.i64
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; CHECK: subs {{x[0-9]+}}, x0, #4
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: uaddo.i32
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; CHECK: adds {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, hs
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: uaddo.i64
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; CHECK: adds {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, hs
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: ssubo1.i32
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; CHECK: subs {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @ssubo2.i32(i32 %v1, i32* %res) {
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entry:
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; CHECK-LABEL: ssubo2.i32
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; CHECK: adds {{w[0-9]+}}, w0, #4
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: ssubo.i64
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; CHECK: subs {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: usubo.i32
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; CHECK: subs {{w[0-9]+}}, w0, w1
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; CHECK-NEXT: cset {{w[0-9]+}}, lo
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: usubo.i64
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; CHECK: subs {{x[0-9]+}}, x0, x1
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; CHECK-NEXT: cset {{w[0-9]+}}, lo
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%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: smulo.i32
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; CHECK: smull x[[MREG:[0-9]+]], w0, w1
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; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
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; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: smulo.i64
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; CHECK: mul [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
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entry:
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; CHECK-LABEL: umulo.i32
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; CHECK: umull [[MREG:x[0-9]+]], w0, w1
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; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32* %res
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ret i1 %obit
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}
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define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
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entry:
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; CHECK-LABEL: umulo.i64
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; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp xzr, [[MREG]]
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64* %res
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ret i1 %obit
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}
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;
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; Check the use of the overflow bit in combination with a select instruction.
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;
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define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: saddo.select.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: csel w0, w0, w1, vs
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: saddo.select.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: csel x0, x0, x1, vs
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: uaddo.select.i32
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; CHECK: cmn w0, w1
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; CHECK-NEXT: csel w0, w0, w1, hs
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%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: uaddo.select.i64
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; CHECK: cmn x0, x1
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; CHECK-NEXT: csel x0, x0, x1, hs
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: ssubo.select.i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: csel w0, w0, w1, vs
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%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: ssubo.select.i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: csel x0, x0, x1, vs
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%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: usubo.select.i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: csel w0, w0, w1, lo
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%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: usubo.select.i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: csel x0, x0, x1, lo
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%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i32
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; CHECK: smull x[[MREG:[0-9]+]], w0, w1
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; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
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; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: smulo.select.i64
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; CHECK: mul [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
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ret i64 %ret
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}
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define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i32
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; CHECK: umull [[MREG:x[0-9]+]], w0, w1
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; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
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; CHECK-NEXT: csel w0, w0, w1, ne
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%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
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%obit = extractvalue {i32, i1} %t, 1
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%ret = select i1 %obit, i32 %v1, i32 %v2
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ret i32 %ret
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}
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define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
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entry:
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; CHECK-LABEL: umulo.select.i64
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; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
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; CHECK-NEXT: cmp xzr, [[MREG]]
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; CHECK-NEXT: csel x0, x0, x1, ne
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%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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%obit = extractvalue {i64, i1} %t, 1
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%ret = select i1 %obit, i64 %v1, i64 %v2
|
|
ret i64 %ret
|
|
}
|
|
|
|
|
|
;
|
|
; Check the use of the overflow bit in combination with a branch instruction.
|
|
;
|
|
define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: saddo.br.i32
|
|
; CHECK: cmn w0, w1
|
|
; CHECK-NEXT: b.vc
|
|
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: saddo.br.i64
|
|
; CHECK: cmn x0, x1
|
|
; CHECK-NEXT: b.vc
|
|
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: uaddo.br.i32
|
|
; CHECK: cmn w0, w1
|
|
; CHECK-NEXT: b.lo
|
|
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: uaddo.br.i64
|
|
; CHECK: cmn x0, x1
|
|
; CHECK-NEXT: b.lo
|
|
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: ssubo.br.i32
|
|
; CHECK: cmp w0, w1
|
|
; CHECK-NEXT: b.vc
|
|
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: ssubo.br.i64
|
|
; CHECK: cmp x0, x1
|
|
; CHECK-NEXT: b.vc
|
|
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: usubo.br.i32
|
|
; CHECK: cmp w0, w1
|
|
; CHECK-NEXT: b.hs
|
|
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: usubo.br.i64
|
|
; CHECK: cmp x0, x1
|
|
; CHECK-NEXT: b.hs
|
|
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: smulo.br.i32
|
|
; CHECK: smull x[[MREG:[0-9]+]], w0, w1
|
|
; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
|
|
; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: smulo.br.i64
|
|
; CHECK: mul [[MREG:x[0-9]+]], x0, x1
|
|
; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
|
|
; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: umulo.br.i32
|
|
; CHECK: umull [[MREG:x[0-9]+]], w0, w1
|
|
; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
|
|
; CHECK-NEXT: b.eq
|
|
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
|
|
%val = extractvalue {i32, i1} %t, 0
|
|
%obit = extractvalue {i32, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
|
|
entry:
|
|
; CHECK-LABEL: umulo.br.i64
|
|
; CHECK: umulh [[REG:x[0-9]+]], x0, x1
|
|
; CHECK-NEXT: {{cbz|cmp}}
|
|
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
|
|
%val = extractvalue {i64, i1} %t, 0
|
|
%obit = extractvalue {i64, i1} %t, 1
|
|
br i1 %obit, label %overflow, label %continue
|
|
|
|
overflow:
|
|
ret i1 false
|
|
|
|
continue:
|
|
ret i1 true
|
|
}
|
|
|
|
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
|
|
declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
|
|
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
|
|
|