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0d9a67f578
Summary: This is preparation for ThunderX processors that have Large System Extension (LSE) atomic instructions, but not the other instructions introduced by V8.1a. This will mimic changes to GCC as described here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html LSE instructions are: LD/ST<op>, CAS*, SWP Reviewers: t.p.northover, echristo, jmolloy, rengolin Subscribers: aemerson, mehdi_amini Differential Revision: https://reviews.llvm.org/D26621 llvm-svn: 288279
347 lines
15 KiB
TableGen
347 lines
15 KiB
TableGen
//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing.
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Subtarget features.
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//
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable cryptographic instructions">;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable ARMv8 CRC-32 checksum instructions">;
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
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def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
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"Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable ARMv8 PMUv3 Performance Monitors extension">;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Full FP16", [FeatureFPARMv8]>;
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def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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"Enable Statistical Profiling extension">;
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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/// Cyclone has instructions which zero registers for "free".
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
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"Reserve X18, making it unavailable "
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"as a GPR">;
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def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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"Use alias analysis during codegen">;
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def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
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"true",
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"balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
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def FeaturePredictableSelectIsExpensive : SubtargetFeature<
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"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
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"Prefer likely predicted branches over selects">;
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def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
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"CustomAsCheapAsMove", "true",
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"Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
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def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
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"UsePostRAScheduler", "true", "Schedule again after register allocation">;
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def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
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"Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
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def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs",
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"AvoidQuadLdStPairs", "true",
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"Do not form quad load/store pair operations">;
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def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
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"alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
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"true", "Use alternative pattern for sextload convert to f32">;
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def FeatureArithmeticBccFusion : SubtargetFeature<
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"arith-bcc-fusion", "HasArithmeticBccFusion", "true",
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"CPU fuses arithmetic+bcc operations">;
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def FeatureArithmeticCbzFusion : SubtargetFeature<
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"arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
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"CPU fuses arithmetic + cbz/cbnz operations">;
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def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
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"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
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"Disable latency scheduling heuristic">;
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def FeatureUseRSqrt : SubtargetFeature<
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"use-reciprocal-square-root", "UseRSqrt", "true",
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"Use the reciprocal square root approximation">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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//
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE]>;
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def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
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"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AArch64RegisterInfo.td"
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include "AArch64CallingConvention.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AArch64Schedule.td"
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include "AArch64InstrInfo.td"
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def AArch64InstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Named operands for MRS/MSR/TLBI/...
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//===----------------------------------------------------------------------===//
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include "AArch64SystemOperands.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Processors supported.
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//
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include "AArch64SchedA53.td"
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include "AArch64SchedA57.td"
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include "AArch64SchedCyclone.td"
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include "AArch64SchedFalkor.td"
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include "AArch64SchedKryo.td"
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include "AArch64SchedM1.td"
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include "AArch64SchedVulcan.td"
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def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", [
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FeatureBalanceFPOps,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureUseAA
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]>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors", [
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FeatureBalanceFPOps,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive
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]>;
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def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
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"Cortex-A72 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
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"Cortex-A73 ARM processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
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"Cyclone", [
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FeatureAlternateSExtLoadCVTF32Pattern,
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FeatureCrypto,
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FeatureDisableLatencySchedHeuristic,
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FeatureFPARMv8,
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FeatureArithmeticBccFusion,
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FeatureArithmeticCbzFusion,
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FeatureNEON,
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FeaturePerfMon,
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FeatureSlowMisaligned128Store,
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FeatureZCRegMove,
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FeatureZCZeroing
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]>;
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def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-M1 processors",
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[FeatureAvoidQuadLdStPairs,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureUseRSqrt,
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FeatureZCZeroing]>;
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def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-M2 processors",
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[FeatureAvoidQuadLdStPairs,
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureZCZeroing]>;
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def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
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"Qualcomm Kryo processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureZCZeroing
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]>;
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def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
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"Qualcomm Falkor processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon
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]>;
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def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
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"Broadcom Vulcan processors", [
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FeatureCRC,
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FeatureCrypto,
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FeatureFPARMv8,
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FeatureArithmeticBccFusion,
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FeatureNEON,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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HasV8_1aOps]>;
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def : ProcessorModel<"generic", NoSchedModel, [
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FeatureCRC,
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FeatureFPARMv8,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler
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]>;
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// FIXME: Cortex-A35 is currently modelled as a Cortex-A53
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def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
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def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
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// FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
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def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
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def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
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def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
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def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
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def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
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def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
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def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def GenericAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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string Name = "generic";
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string BreakCharacters = ".";
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}
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def AppleAsmParserVariant : AsmParserVariant {
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int Variant = 1;
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string Name = "apple-neon";
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string BreakCharacters = ".";
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}
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// AArch64 Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def GenericAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def AppleAsmWriter : AsmWriter {
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let AsmWriterClassName = "AppleInstPrinter";
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int PassSubtarget = 1;
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int Variant = 1;
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int isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def AArch64 : Target {
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let InstructionSet = AArch64InstrInfo;
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let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
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let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
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}
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