Simon Pilgrim 4d4989655e [X86][SSE1] Add MOVLHPS/MOVHLPS lowering and memory folding support ... As discussed on PR26491, this patch adds support for lowering v4f32 shuffles to the MOVLHPS/MOVHLPS instructions. It also adds support for memory folding with their MOVLPS/MOVHPS load equivalents. This first patch only really helps SSE1 targets as SSE2+ targets will widen the shuffle mask and use v2f64 equivalents (although they still combine to MOVLHPS/MOVHLPS for v2f64 splats). This will have to be addressed in a future patch, most likely when we add support for binary target shuffle combines. Differential Revision: http://reviews.llvm.org/D16956 llvm-svn: 260168		2016-02-08 23:03:46 +00:00
..
AArch64	AArch64: match correct order in subtraction pattern.	2016-02-08 19:33:18 +00:00
AMDGPU	AMDGPU: Remove bfi and bfm intrinsics	2016-02-08 19:06:01 +00:00
ARM	ARM: support TLS for WoA	2016-02-03 18:21:59 +00:00
BPF
CPP
Generic	Remove autoconf support	2016-01-26 21:29:08 +00:00
Hexagon	The canonical way to XFAIL a test for all targets is XFAIL: *, not XFAIL:	2016-02-04 16:21:38 +00:00
Inputs
Mips	[mips] Add SHF_MIPS_GPREL flag to the MIPS .sbss and .sdata sections	2016-02-03 11:50:22 +00:00
MIR
MSP430
NVPTX	[NVPTX] Disable performance optimizations when OptLevel==None	2016-02-04 04:15:36 +00:00
PowerPC	Add the missing test case for PR26193	2016-02-05 15:03:17 +00:00
SPARC
SystemZ	[SystemZ] Fix wrong-code generation for certain always-false conditions	2016-02-01 18:31:19 +00:00
Thumb	[MC] Use .p2align instead of .align	2016-01-26 00:03:25 +00:00
Thumb2	[SCEV] Try to reuse existing value during SCEV expansion	2016-02-04 01:27:38 +00:00
WebAssembly	[WebAssembly] Update the br_if instructions' operand orders to match the spec.	2016-02-08 21:50:13 +00:00
WinEH	Revert r258580 and r258581.	2016-02-01 03:29:38 +00:00
X86	[X86][SSE1] Add MOVLHPS/MOVHLPS lowering and memory folding support	2016-02-08 23:03:46 +00:00
XCore	[MC] Use .p2align instead of .align	2016-01-26 00:03:25 +00:00