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3d390604c7
This patch is a follow-up to r338702. We don't need to use a map to model the wait/ready/issued sets. It is much more efficient to use a vector instead. This patch gives us an average 7.5% speedup (on top of the ~12% speedup obtained after r338702). llvm-svn: 338883
476 lines
18 KiB
C++
476 lines
18 KiB
C++
//===--------------------- Scheduler.h ------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// A scheduler for Processor Resource Units and Processor Resource Groups.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
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#define LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
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#include "HWEventListener.h"
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#include "HardwareUnit.h"
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#include "Instruction.h"
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#include "LSUnit.h"
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#include "RetireControlUnit.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include <map>
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namespace mca {
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/// Used to notify the internal state of a processor resource.
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///
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/// A processor resource is available if it is not reserved, and there are
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/// available slots in the buffer. A processor resource is unavailable if it
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/// is either reserved, or the associated buffer is full. A processor resource
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/// with a buffer size of -1 is always available if it is not reserved.
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///
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/// Values of type ResourceStateEvent are returned by method
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/// ResourceState::isBufferAvailable(), which is used to query the internal
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/// state of a resource.
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///
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/// The naming convention for resource state events is:
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/// * Event names start with prefix RS_
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/// * Prefix RS_ is followed by a string describing the actual resource state.
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enum ResourceStateEvent {
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RS_BUFFER_AVAILABLE,
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RS_BUFFER_UNAVAILABLE,
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RS_RESERVED
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};
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/// A descriptor for processor resources.
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///
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/// Each object of class ResourceState is associated to a specific processor
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/// resource. There is an instance of this class for every processor resource
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/// defined by the scheduling model.
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/// A ResourceState dynamically tracks the availability of units of a processor
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/// resource. For example, the ResourceState of a ProcResGroup tracks the
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/// availability of resource units which are part of the group.
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///
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/// Internally, ResourceState uses a round-robin selector to identify
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/// which unit of the group shall be used next.
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class ResourceState {
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// Index to the MCProcResourceDesc in the processor Model.
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unsigned ProcResourceDescIndex;
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// A resource mask. This is generated by the tool with the help of
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// function `mca::createProcResourceMasks' (see Support.h).
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uint64_t ResourceMask;
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// A ProcResource can specify a number of units. For the purpose of dynamic
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// scheduling, a processor resource with more than one unit behaves like a
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// group. This field has one bit set for every unit/resource that is part of
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// the group.
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// For groups, this field defaults to 'ResourceMask'. For non-group
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// resources, the number of bits set in this mask is equivalent to the
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// number of units (i.e. field 'NumUnits' in 'ProcResourceUnits').
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uint64_t ResourceSizeMask;
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// A simple round-robin selector for processor resources.
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// Each bit of the mask identifies a sub resource within this group.
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//
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// As an example, lets assume that this ResourceState describes a
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// processor resource group composed of the following three units:
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// ResourceA -- 0b001
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// ResourceB -- 0b010
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// ResourceC -- 0b100
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//
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// Each unit is identified by a ResourceMask which always contains a
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// single bit set. Field NextInSequenceMask is initially set to value
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// 0xb111. That value is obtained by OR'ing the resource masks of
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// processor resource that are part of the group.
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//
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// NextInSequenceMask -- 0b111
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//
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// Field NextInSequenceMask is used by the resource manager (i.e.
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// an object of class ResourceManager) to select the "next available resource"
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// from the set. The algorithm would prioritize resources with a bigger
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// ResourceMask value.
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//
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// In this example, there are three resources in the set, and 'ResourceC'
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// has the highest mask value. The round-robin selector would firstly select
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// 'ResourceC', then 'ResourceB', and eventually 'ResourceA'.
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//
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// When a resource R is used, its corresponding bit is cleared from the set.
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//
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// Back to the example:
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// If 'ResourceC' is selected, then the new value of NextInSequenceMask
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// becomes 0xb011.
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//
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// When NextInSequenceMask becomes zero, it is reset to its original value
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// (in this example, that value would be 0b111).
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uint64_t NextInSequenceMask;
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// Some instructions can only be issued on very specific pipeline resources.
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// For those instructions, we know exactly which resource would be consumed
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// without having to dynamically select it using field 'NextInSequenceMask'.
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//
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// The resource mask bit associated to the (statically) selected
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// processor resource is still cleared from the 'NextInSequenceMask'.
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// If that bit was already zero in NextInSequenceMask, then we update
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// mask 'RemovedFromNextInSequence'.
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//
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// When NextInSequenceMask is reset back to its initial value, the algorithm
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// removes any bits which are set in RemoveFromNextInSequence.
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uint64_t RemovedFromNextInSequence;
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// A mask of ready units.
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uint64_t ReadyMask;
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// Buffered resources will have this field set to a positive number bigger
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// than 0. A buffered resource behaves like a separate reservation station
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// implementing its own buffer for out-of-order execution.
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// A buffer of 1 is for units that force in-order execution.
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// A value of 0 is treated specially. In particular, a resource with
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// A BufferSize = 0 is for an in-order issue/dispatch resource.
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// That means, this resource is reserved starting from the dispatch event,
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// until all the "resource cycles" are consumed after the issue event.
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// While this resource is reserved, no other instruction may be dispatched.
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int BufferSize;
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// Available slots in the buffer (zero, if this is not a buffered resource).
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unsigned AvailableSlots;
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// True if this is resource is currently unavailable.
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// An instruction may "reserve" a resource for a number of cycles.
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// During those cycles, the reserved resource cannot be used for other
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// instructions, even if the ReadyMask is set.
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bool Unavailable;
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bool isSubResourceReady(uint64_t ID) const { return ReadyMask & ID; }
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/// Returns the mask identifier of the next available resource in the set.
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uint64_t getNextInSequence() const {
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assert(NextInSequenceMask);
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return llvm::PowerOf2Floor(NextInSequenceMask);
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}
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/// Returns the mask of the next available resource within the set,
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/// and updates the resource selector.
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void updateNextInSequence() {
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NextInSequenceMask ^= getNextInSequence();
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if (!NextInSequenceMask)
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NextInSequenceMask = ResourceSizeMask;
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}
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uint64_t computeResourceSizeMaskForGroup(uint64_t ResourceMask) {
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assert(llvm::countPopulation(ResourceMask) > 1);
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return ResourceMask ^ llvm::PowerOf2Floor(ResourceMask);
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}
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public:
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ResourceState(const llvm::MCProcResourceDesc &Desc, unsigned Index,
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uint64_t Mask)
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: ProcResourceDescIndex(Index), ResourceMask(Mask) {
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bool IsAGroup = llvm::countPopulation(ResourceMask) > 1;
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ResourceSizeMask = IsAGroup ? computeResourceSizeMaskForGroup(ResourceMask)
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: ((1ULL << Desc.NumUnits) - 1);
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NextInSequenceMask = ResourceSizeMask;
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RemovedFromNextInSequence = 0;
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ReadyMask = ResourceSizeMask;
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BufferSize = Desc.BufferSize;
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AvailableSlots = BufferSize == -1 ? 0U : static_cast<unsigned>(BufferSize);
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Unavailable = false;
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}
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unsigned getProcResourceID() const { return ProcResourceDescIndex; }
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uint64_t getResourceMask() const { return ResourceMask; }
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int getBufferSize() const { return BufferSize; }
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bool isBuffered() const { return BufferSize > 0; }
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bool isInOrder() const { return BufferSize == 1; }
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bool isADispatchHazard() const { return BufferSize == 0; }
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bool isReserved() const { return Unavailable; }
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void setReserved() { Unavailable = true; }
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void clearReserved() { Unavailable = false; }
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// A resource is ready if it is not reserved, and if there are enough
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// available units.
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// If a resource is also a dispatch hazard, then we don't check if
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// it is reserved because that check would always return true.
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// A resource marked as "dispatch hazard" is always reserved at
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// dispatch time. When this method is called, the assumption is that
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// the user of this resource has been already dispatched.
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bool isReady(unsigned NumUnits = 1) const {
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return (!isReserved() || isADispatchHazard()) &&
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llvm::countPopulation(ReadyMask) >= NumUnits;
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}
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bool isAResourceGroup() const {
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return llvm::countPopulation(ResourceMask) > 1;
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}
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bool containsResource(uint64_t ID) const { return ResourceMask & ID; }
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void markSubResourceAsUsed(uint64_t ID) {
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assert(isSubResourceReady(ID));
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ReadyMask ^= ID;
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}
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void releaseSubResource(uint64_t ID) {
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assert(!isSubResourceReady(ID));
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ReadyMask ^= ID;
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}
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unsigned getNumUnits() const {
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return isAResourceGroup() ? 1U : llvm::countPopulation(ResourceSizeMask);
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}
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uint64_t selectNextInSequence();
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void removeFromNextInSequence(uint64_t ID);
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ResourceStateEvent isBufferAvailable() const {
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if (isADispatchHazard() && isReserved())
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return RS_RESERVED;
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if (!isBuffered() || AvailableSlots)
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return RS_BUFFER_AVAILABLE;
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return RS_BUFFER_UNAVAILABLE;
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}
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void reserveBuffer() {
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if (AvailableSlots)
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AvailableSlots--;
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}
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void releaseBuffer() {
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if (BufferSize > 0)
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AvailableSlots++;
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assert(AvailableSlots <= static_cast<unsigned>(BufferSize));
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}
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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/// A resource unit identifier.
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///
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/// This is used to identify a specific processor resource unit using a pair
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/// of indices where the 'first' index is a processor resource mask, and the
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/// 'second' index is an index for a "sub-resource" (i.e. unit).
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typedef std::pair<uint64_t, uint64_t> ResourceRef;
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// First: a MCProcResourceDesc index identifying a buffered resource.
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// Second: max number of buffer entries used in this resource.
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typedef std::pair<unsigned, unsigned> BufferUsageEntry;
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/// A resource manager for processor resource units and groups.
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///
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/// This class owns all the ResourceState objects, and it is responsible for
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/// acting on requests from a Scheduler by updating the internal state of
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/// ResourceState objects.
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/// This class doesn't know about instruction itineraries and functional units.
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/// In future, it can be extended to support itineraries too through the same
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/// public interface.
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class ResourceManager {
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// The resource manager owns all the ResourceState.
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using UniqueResourceState = std::unique_ptr<ResourceState>;
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std::vector<UniqueResourceState> Resources;
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// Keeps track of which resources are busy, and how many cycles are left
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// before those become usable again.
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llvm::SmallDenseMap<ResourceRef, unsigned> BusyResources;
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// A table to map processor resource IDs to processor resource masks.
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llvm::SmallVector<uint64_t, 8> ProcResID2Mask;
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// Populate resource descriptors.
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void initialize(const llvm::MCSchedModel &SM);
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// Returns the actual resource unit that will be used.
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ResourceRef selectPipe(uint64_t ResourceID);
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void use(const ResourceRef &RR);
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void release(const ResourceRef &RR);
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unsigned getNumUnits(uint64_t ResourceID) const;
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public:
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ResourceManager(const llvm::MCSchedModel &SM)
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: ProcResID2Mask(SM.getNumProcResourceKinds()) {
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initialize(SM);
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}
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// Returns RS_BUFFER_AVAILABLE if buffered resources are not reserved, and if
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// there are enough available slots in the buffers.
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ResourceStateEvent canBeDispatched(llvm::ArrayRef<uint64_t> Buffers) const;
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// Return the processor resource identifier associated to this Mask.
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unsigned resolveResourceMask(uint64_t Mask) const;
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// Consume a slot in every buffered resource from array 'Buffers'. Resource
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// units that are dispatch hazards (i.e. BufferSize=0) are marked as reserved.
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void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers);
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// Release buffer entries previously allocated by method reserveBuffers.
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void releaseBuffers(llvm::ArrayRef<uint64_t> Buffers);
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// Reserve a processor resource. A reserved resource is not available for
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// instruction issue until it is released.
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void reserveResource(uint64_t ResourceID);
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// Release a previously reserved processor resource.
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void releaseResource(uint64_t ResourceID);
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// Returns true if all resources are in-order, and there is at least one
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// resource which is a dispatch hazard (BufferSize = 0).
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bool mustIssueImmediately(const InstrDesc &Desc);
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bool canBeIssued(const InstrDesc &Desc) const;
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void issueInstruction(
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const InstrDesc &Desc,
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llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
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void cycleEvent(llvm::SmallVectorImpl<ResourceRef> &ResourcesFreed);
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#ifndef NDEBUG
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void dump() const {
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for (const UniqueResourceState &Resource : Resources)
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Resource->dump();
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}
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#endif
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}; // namespace mca
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/// Class Scheduler is responsible for issuing instructions to pipeline
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/// resources.
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///
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/// Internally, it delegates to a ResourceManager the management of processor
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/// resources. This class is also responsible for tracking the progress of
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/// instructions from the dispatch stage, until the write-back stage.
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///
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/// An instruction dispatched to the Scheduler is initially placed into either
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/// the 'WaitSet' or the 'ReadySet' depending on the availability of the input
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/// operands.
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///
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/// An instruction is moved from the WaitSet to the ReadySet when register
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/// operands become available, and all memory dependencies are met.
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/// Instructions that are moved from the WaitSet to the ReadySet transition
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/// in state from 'IS_AVAILABLE' to 'IS_READY'.
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///
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/// On every cycle, the Scheduler checks if it can promote instructions from the
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/// WaitSet to the ReadySet.
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///
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/// An Instruction is moved from the ReadySet the `IssuedSet` when it is issued
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/// to a (one or more) pipeline(s). This event also causes an instruction state
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/// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
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/// leaves the IssuedSet when it reaches the write-back stage.
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class Scheduler : public HardwareUnit {
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const llvm::MCSchedModel &SM;
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// Hardware resources that are managed by this scheduler.
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std::unique_ptr<ResourceManager> Resources;
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std::unique_ptr<LSUnit> LSU;
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std::vector<InstRef> WaitSet;
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std::vector<InstRef> ReadySet;
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std::vector<InstRef> IssuedSet;
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/// Issue an instruction without updating the ready queue.
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void issueInstructionImpl(
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InstRef &IR,
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llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Pipes);
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public:
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Scheduler(const llvm::MCSchedModel &Model, unsigned LoadQueueSize,
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unsigned StoreQueueSize, bool AssumeNoAlias)
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: SM(Model), Resources(llvm::make_unique<ResourceManager>(SM)),
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LSU(llvm::make_unique<LSUnit>(LoadQueueSize, StoreQueueSize,
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AssumeNoAlias)) {}
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/// Check if the instruction in 'IR' can be dispatched.
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///
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/// The DispatchStage is responsible for querying the Scheduler before
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/// dispatching new instructions. This routine is used for performing such
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/// a query. If the instruction 'IR' can be dispatched, then true is
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/// returned, otherwise false is returned with Event set to the stall type.
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bool canBeDispatched(const InstRef &IR,
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HWStallEvent::GenericEventType &Event) const;
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/// Returns true if there is availibility for IR in the LSU.
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bool isReady(const InstRef &IR) const { return LSU->isReady(IR); }
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/// Issue an instruction. The Used container is populated with
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/// the resource objects consumed on behalf of issuing this instruction.
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void
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issueInstruction(InstRef &IR,
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llvm::SmallVectorImpl<std::pair<ResourceRef, double>> &Used);
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/// This routine will attempt to issue an instruction immediately (for
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/// zero-latency instructions).
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///
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/// Returns true if the instruction is issued immediately. If this does not
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/// occur, then the instruction will be added to the Scheduler's ReadySet.
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bool issueImmediately(InstRef &IR);
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/// Reserve one entry in each buffered resource.
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void reserveBuffers(llvm::ArrayRef<uint64_t> Buffers) {
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Resources->reserveBuffers(Buffers);
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}
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/// Release buffer entries previously allocated by method reserveBuffers.
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void releaseBuffers(llvm::ArrayRef<uint64_t> Buffers) {
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Resources->releaseBuffers(Buffers);
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}
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/// Update the resources managed by the scheduler.
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/// This routine is to be called at the start of a new cycle, and is
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/// responsible for updating scheduler resources. Resources are released
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/// once they have been fully consumed.
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void reclaimSimulatedResources(llvm::SmallVectorImpl<ResourceRef> &Freed);
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/// Move instructions from the WaitSet to the ReadySet if input operands
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/// are all available.
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void promoteToReadySet(llvm::SmallVectorImpl<InstRef> &Ready);
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/// Update the ready queue.
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void updatePendingQueue(llvm::SmallVectorImpl<InstRef> &Ready);
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/// Update the issued queue.
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void updateIssuedSet(llvm::SmallVectorImpl<InstRef> &Executed);
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/// Updates the Scheduler's resources to reflect that an instruction has just
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/// been executed.
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void onInstructionExecuted(const InstRef &IR);
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/// Obtain the processor's resource identifier for the given
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/// resource mask.
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unsigned getResourceID(uint64_t Mask) {
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return Resources->resolveResourceMask(Mask);
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}
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/// Reserve resources necessary to issue the instruction.
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/// Returns true if the resources are ready and the (LSU) can
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/// execute the given instruction immediately.
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bool reserveResources(InstRef &IR);
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/// Select the next instruction to issue from the ReadySet.
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/// This method gives priority to older instructions.
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InstRef select();
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#ifndef NDEBUG
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// Update the ready queues.
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void dump() const;
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// This routine performs a sanity check. This routine should only be called
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// when we know that 'IR' is not in the scheduler's instruction queues.
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void sanityCheck(const InstRef &IR) const {
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assert(llvm::find(WaitSet, IR) == WaitSet.end());
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assert(llvm::find(ReadySet, IR) == ReadySet.end());
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assert(llvm::find(IssuedSet, IR) == IssuedSet.end());
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}
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#endif // !NDEBUG
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};
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} // namespace mca
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#endif // LLVM_TOOLS_LLVM_MCA_SCHEDULER_H
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