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https://github.com/RPCS3/llvm-mirror.git
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1c9d5cdeab
Summary: The machine instruction scheduler was illegally moving a buffer store past a buffer load with the same descriptor and offset. Fixed by marking buffer ops as mayAlias and isAliased. This may be overly conservative, and we may need to revisit. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D43332 Change-Id: Iff3173d9e0653e830474546276ab9d30318b8ef7 llvm-svn: 325567
54 lines
2.9 KiB
LLVM
54 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The buffer_loads and buffer_stores all access the same location. Check they do
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; not get reordered by the scheduler.
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; GCN-LABEL: {{^}}_amdgpu_cs_main:
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; GCN: buffer_load_dword
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; GCN: buffer_store_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dword
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; Function Attrs: nounwind
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define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> inreg %arg3, <3 x i32> %arg5) {
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.entry:
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%tmp9 = add <3 x i32> %arg3, %arg5
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%tmp10 = extractelement <3 x i32> %tmp9, i32 0
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%tmp11 = shl i32 %tmp10, 2
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%tmp12 = inttoptr i64 undef to <4 x i32> addrspace(4)*
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%tmp13 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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%tmp14 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %tmp13, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp17 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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call void @llvm.amdgcn.buffer.store.f32(float %tmp14, <4 x i32> %tmp17, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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%tmp21 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp22 = fadd reassoc nnan arcp contract float %tmp21, 1.000000e+00
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call void @llvm.amdgcn.buffer.store.f32(float %tmp22, <4 x i32> %tmp20, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp25 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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%tmp26 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %tmp25, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp27 = fadd reassoc nnan arcp contract float %tmp26, 1.000000e+00
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call void @llvm.amdgcn.buffer.store.f32(float %tmp27, <4 x i32> %tmp25, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp30 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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%tmp31 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %tmp30, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp32 = fadd reassoc nnan arcp contract float %tmp31, 1.000000e+00
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call void @llvm.amdgcn.buffer.store.f32(float %tmp32, <4 x i32> %tmp30, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp35 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp12, align 16
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%tmp36 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %tmp35, i32 0, i32 %tmp11, i1 false, i1 false) #0
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%tmp37 = fadd reassoc nnan arcp contract float %tmp36, 1.000000e+00
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call void @llvm.amdgcn.buffer.store.f32(float %tmp37, <4 x i32> %tmp35, i32 0, i32 %tmp11, i1 false, i1 false) #0
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ret void
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}
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declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #2
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #3
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attributes #2 = { nounwind readonly }
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attributes #3 = { nounwind writeonly }
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