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133 lines
5.1 KiB
LLVM
133 lines
5.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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@lds.obj = addrspace(3) global [256 x i32] undef, align 4
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; GCN-LABEL: {{^}}write_ds_sub0_offset0_global:
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; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0
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; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]]
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; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]]
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; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b
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; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12
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define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 {
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entry:
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
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%sub1 = sub i32 0, %x.i
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%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
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%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
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store i32 123, i32 addrspace(3)* %arrayidx
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535
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define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 65535, %shl
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%ptr = inttoptr i32 %add to i8 addrspace(3)*
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store i8 13, i8 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x10000, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN: ds_write_b8 [[NEG]], [[K]]{{$}}
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define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 65536, %shl
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%ptr = inttoptr i32 %add to i8 addrspace(3)*
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store i8 13, i8 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}}
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; GCN: s_endpgm
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define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add0 = add i32 123, %shl
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%add1 = add i32 456, %shl
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%ptr0 = inttoptr i32 %add0 to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr0
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%ptr1 = inttoptr i32 %add1 to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr1
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN-NOT: v_sub
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; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}}
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; GCN: s_endpgm
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define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 123, %shl
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%ptr = inttoptr i32 %add to i32 addrspace(3)*
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store volatile i32 13, i32 addrspace(3)* %ptr
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store volatile i32 13, i32 addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]]
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; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255
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define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 1019, %shl
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%ptr = inttoptr i32 %add to i64 addrspace(3)*
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store i64 123, i64 addrspace(3)* %ptr, align 4
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]]
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; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 1020, %shl
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%ptr = inttoptr i32 %add to i64 addrspace(3)*
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store i64 123, i64 addrspace(3)* %ptr, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind convergent }
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