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https://github.com/RPCS3/llvm-mirror.git
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141144803d
This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable. It performs: AND s0, s0, ~(1 << n) -> BITSET0 s0, n OR s0, s0, (1 << n) -> BITSET1 s0, n AND s0, s1, x -> ANDN2 s0, s1, ~x OR s0, s1, x -> ORN2 s0, s1, ~x XOR s0, s1, x -> XNOR s0, s1, ~x In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31). llvm-svn: 348601
114 lines
4.4 KiB
LLVM
114 lines
4.4 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32:
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; SI-NOT: and
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; SI: v_sub_f32_e64 {{v[0-9]+}}, {{v[0-9]+}}, |{{s[0-9]+}}|
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define amdgpu_kernel void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fadd = fadd float %y, %fsub
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store float %fadd, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32:
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; SI-NOT: and
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; SI: v_mul_f32_e64 {{v[0-9]+}}, {{v[0-9]+}}, -|{{s[0-9]+}}|
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; SI-NOT: and
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define amdgpu_kernel void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
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%fabs = call float @llvm.fabs.f32(float %x)
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%fsub = fsub float -0.000000e+00, %fabs
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%fmul = fmul float %y, %fsub
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store float %fmul, float addrspace(1)* %out, align 4
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ret void
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}
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; FUNC-LABEL: {{^}}fneg_fabs_free_f32:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; VI: s_bitset1_b32 s{{[0-9]+}}, 31
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define amdgpu_kernel void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define amdgpu_kernel void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_f32:
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define amdgpu_kernel void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_fneg_fabs_f32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define amdgpu_kernel void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%val = load float, float addrspace(1)* %in, align 4
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%fabs = call float @llvm.fabs.f32(float %val)
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%fsub = fsub float -0.000000e+00, %fabs
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store float %fsub, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v2f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: -PV
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: -PV
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; FIXME: In this case two uses of the constant should be folded
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; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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define amdgpu_kernel void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
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store <2 x float> %fsub, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
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; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, [[SIGNBITK]], v{{[0-9]+}}
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define amdgpu_kernel void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
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store <4 x float> %fsub, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @fabs(float) readnone
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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