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99 lines
3.2 KiB
LLVM
99 lines
3.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}s_fneg_f32:
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; R600: -PV
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; GCN: v_xor_b32
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define amdgpu_kernel void @s_fneg_f32(float addrspace(1)* %out, float %in) {
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%fneg = fsub float -0.000000e+00, %in
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store float %fneg, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_fneg_v2f32:
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; R600: -PV
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; R600: -PV
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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define amdgpu_kernel void @s_fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
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%fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
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store <2 x float> %fneg, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_fneg_v4f32:
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; R600: -PV
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; R600: -T
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; R600: -PV
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; R600: -PV
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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define amdgpu_kernel void @s_fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
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%fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
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store <4 x float> %fneg, <4 x float> addrspace(1)* %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; FUNC-LABEL: {{^}}fsub0_f32:
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; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
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; R600-NOT: XOR
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; R600: -KC0[2].Z
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define amdgpu_kernel void @fsub0_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fsub = fsub float 0.0, %bc
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_free_f32:
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; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN: v_bfrev_b32_e32 [[SIGNBIT:v[0-9]+]], 1{{$}}
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; GCN: v_xor_b32_e32 [[RES:v[0-9]+]], [[NEG_VALUE]], [[SIGNBIT]]
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; GCN: buffer_store_dword [[RES]]
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; R600-NOT: XOR
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; R600: -PV.W
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define amdgpu_kernel void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fsub = fsub float -0.0, %bc
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store float %fsub, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fold_f32:
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; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-NOT: xor
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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define amdgpu_kernel void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
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%fsub = fsub float -0.0, %in
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%fmul = fmul float %fsub, %in
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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; Make sure we turn some integer operations back into fabs
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; FUNC-LABEL: {{^}}bitpreserve_fneg_f32:
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -4.0
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define amdgpu_kernel void @bitpreserve_fneg_f32(float addrspace(1)* %out, float %in) {
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%in.bc = bitcast float %in to i32
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%int.abs = xor i32 %in.bc, 2147483648
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%bc = bitcast i32 %int.abs to float
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%fadd = fmul float %bc, 4.0
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store float %fadd, float addrspace(1)* %out
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ret void
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}
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