mirror of
https://github.com/RPCS3/llvm-mirror.git
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c4074ba685
Also revert fix r347876 One of the buildbots was reporting a failure in some relevant tests that I can't repro or explain at present, so reverting until I can isolate. llvm-svn: 347911
129 lines
5.5 KiB
LLVM
129 lines
5.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; GCN-LABEL: {{^}}load.f16.1d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16
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define amdgpu_ps <4 x half> @load.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v2f16.1d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v3f16.1d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v4f16.1d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
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define amdgpu_ps <4 x half> @load.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.f16.2d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16
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define amdgpu_ps <4 x half> @load.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v2f16.2d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v3f16.2d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v4f16.2d:
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; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
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define amdgpu_ps <4 x half> @load.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.f16.3d:
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; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x1 unorm a16 d16
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define amdgpu_ps <4 x half> @load.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v2f16.3d:
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; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v3f16.3d:
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; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm a16 d16
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define amdgpu_ps <4 x half> @load.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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; GCN-LABEL: {{^}}load.v4f16.3d:
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; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm a16 d16
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define amdgpu_ps <4 x half> @load.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x half> %v
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}
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declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32, i16, <8 x i32>, i32, i32) #2
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declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32, i16, i16, <8 x i32>, i32, i32) #2
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declare <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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