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734b898f0d
Summary: Instead of writing boolean values temporarily into 32-bit VGPRs if they are involved in PHIs or are observed from outside a loop, we use bitwise masking operations to combine lane masks in a way that is consistent with wave control flow. Move SIFixSGPRCopies to before this pass, since that pass incorrectly attempts to move SGPR phis to VGPRs. This should recover most of the code quality that was lost with the bug fix in "AMDGPU: Remove PHI loop condition optimization". There are still some relevant cases where code quality could be improved, in particular: - We often introduce redundant masks with EXEC. Ideally, we'd have a generic computeKnownBits-like analysis to determine whether masks are already masked by EXEC, so we can avoid this masking both here and when lowering uniform control flow. - The criterion we use to determine whether a def is observed from outside a loop is conservative: it doesn't check whether (loop) branch conditions are uniform. Change-Id: Ibabdb373a7510e426b90deef00f5e16c5d56e64b Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, t-tye, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D53496 llvm-svn: 345719
48 lines
1.3 KiB
LLVM
48 lines
1.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}sub_var_var_i1:
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; GCN: s_xor_b64
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define amdgpu_kernel void @sub_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
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%a = load volatile i1, i1 addrspace(1)* %in0
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%b = load volatile i1, i1 addrspace(1)* %in1
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%sub = sub i1 %a, %b
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store i1 %sub, i1 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}sub_var_imm_i1:
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; GCN: s_not_b64
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define amdgpu_kernel void @sub_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
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%a = load volatile i1, i1 addrspace(1)* %in
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%sub = sub i1 %a, 1
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store i1 %sub, i1 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}sub_i1_cf:
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; GCN: ; %endif
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; GCN: s_not_b64
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define amdgpu_kernel void @sub_i1_cf(i1 addrspace(1)* %out, i1 addrspace(1)* %a, i1 addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%d_cmp = icmp ult i32 %tid, 16
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br i1 %d_cmp, label %if, label %else
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if:
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%0 = load volatile i1, i1 addrspace(1)* %a
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br label %endif
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else:
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%1 = load volatile i1, i1 addrspace(1)* %b
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br label %endif
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endif:
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%2 = phi i1 [%0, %if], [%1, %else]
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%3 = sub i1 %2, -1
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store i1 %3, i1 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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