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252673a9d9
See https://reviews.llvm.org/D47106 for details. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47171 This commit drops that patch's changes to: llvm/test/CodeGen/NVPTX/f16x2-instructions.ll llvm/test/CodeGen/NVPTX/param-load-store.ll For some reason, the dos line endings there prevent me from commiting via the monorepo. A follow-up commit (not via the monorepo) will finish the patch. llvm-svn: 336843
342 lines
9.0 KiB
LLVM
342 lines
9.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap --check-prefix=EG --check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test_udivrem:
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; EG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG: CNDE_INT
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; EG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG: CNDE_INT
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; EG: MULHI
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; EG: MULLO_INT
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; EG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
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; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
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; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]
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; SI-DAG: v_sub_{{[iu]}}32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]
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; SI: v_cmp_eq_u32_e64 [[CC1:s\[[0-9:]+\]]], 0, [[RCP_HI]]
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; SI: v_cndmask_b32_e64 [[CND1:v[0-9]+]], [[RCP_LO]], [[NEG_RCP_LO]], [[CC1]]
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; SI: v_mul_hi_u32 [[E:v[0-9]+]], [[CND1]], [[RCP]]
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; SI-DAG: v_add_{{[iu]}}32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
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; SI-DAG: v_subrev_{{[iu]}}32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
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; SI: v_cndmask_b32_e64 [[CND2:v[0-9]+]], [[RCP_S_E]], [[RCP_A_E]], [[CC1]]
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; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]], [[CND2]],
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; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]], [[CND2]]
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; SI-DAG: v_add_{{[iu]}}32_e32 [[Quotient_A_One:v[0-9]+]], vcc, 1, [[Quotient]]
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; SI-DAG: v_sub_{{[iu]}}32_e32 [[Remainder:v[0-9]+]], vcc, {{[vs][0-9]+}}, [[Num_S_Remainder]]
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Quotient_S_One:v[0-9]+]],
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; SI-DAG: v_subrev_{{[iu]}}32_e32 [[Remainder_S_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32 [[Remainder_A_Den:v[0-9]+]],
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-NOT: v_and_b32
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; SI: s_endpgm
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define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) {
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%result0 = udiv i32 %x, %y
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store i32 %result0, i32 addrspace(1)* %out0
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%result1 = urem i32 %x, %y
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store i32 %result1, i32 addrspace(1)* %out1
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ret void
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}
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; FUNC-LABEL: {{^}}test_udivrem_v2:
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; For SI, we used to have checks for the input and output registers
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; of the instructions, but these are way too fragile. The division for
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; the two vector elements can be intermixed which makes it impossible to
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; accurately check all the operands.
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-NOT: v_and_b32
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; SI: s_endpgm
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define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
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%result0 = udiv <2 x i32> %x, %y
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store <2 x i32> %result0, <2 x i32> addrspace(1)* %out
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%result1 = urem <2 x i32> %x, %y
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store <2 x i32> %result1, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test_udivrem_v4:
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: RECIP_UINT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: MULHI
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; EG-DAG: MULLO_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SETGE_UINT
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; EG-DAG: SETGE_UINT
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; EG-DAG: AND_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: ADD_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_rcp_iflag_f32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_sub_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_add_{{[iu]}}32_e32
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; SI-DAG: v_subrev_{{[iu]}}32_e32
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; SI-DAG: v_cndmask_b32_e64
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; SI-NOT: v_and_b32
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; SI: s_endpgm
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define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
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%result0 = udiv <4 x i32> %x, %y
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store <4 x i32> %result0, <4 x i32> addrspace(1)* %out
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%result1 = urem <4 x i32> %x, %y
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store <4 x i32> %result1, <4 x i32> addrspace(1)* %out
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ret void
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}
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