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9b9b32a724
Summary: This is required for GPUs with 16 bit instructions where f16 is a legal register type and hence int_to_fp i1 to f16 is not lowered by legalizing. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52018 Change-Id: Ie4c0fd6ced7cf10ad612023c6879724d9ded5851 llvm-svn: 342558
115 lines
3.6 KiB
LLVM
115 lines
3.6 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}uitofp_i16_to_f16
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; GCN: buffer_load_ushort v[[A_I16:[0-9]+]]
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; SI: v_cvt_f32_u32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
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; VI: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]]
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; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_i16_to_f16(
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half addrspace(1)* %r,
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i16 addrspace(1)* %a) {
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entry:
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%a.val = load i16, i16 addrspace(1)* %a
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%r.val = uitofp i16 %a.val to half
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}uitofp_i32_to_f16
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; GCN: buffer_load_dword v[[A_I32:[0-9]+]]
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; GCN: v_cvt_f32_u32_e32 v[[A_I16:[0-9]+]], v[[A_I32]]
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; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_I16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_i32_to_f16(
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half addrspace(1)* %r,
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i32 addrspace(1)* %a) {
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entry:
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%a.val = load i32, i32 addrspace(1)* %a
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%r.val = uitofp i32 %a.val to half
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; f16 = uitofp i64 is in uint_to_fp.i64.ll
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; GCN-LABEL: {{^}}uitofp_v2i16_to_v2f16
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; GCN: buffer_load_dword
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; SI-DAG: v_lshlrev_b32_e32
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; SI: v_or_b32_e32
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; VI-DAG: v_cvt_f16_f32_e32
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; VI-DAG: v_cvt_f32_i32_sdwa
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; VI-DAG: v_cvt_f32_i32_sdwa
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; VI-DAG: v_cvt_f16_f32_sdwa
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; VI: v_or_b32_e32
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_v2i16_to_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x i16> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a
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%r.val = uitofp <2 x i16> %a.val to <2 x half>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}uitofp_v2i32_to_v2f16
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; GCN: buffer_load_dwordx2
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f16_f32_e32
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; SI: v_cvt_f16_f32_e32
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; SI-DAG: v_lshlrev_b32_e32
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; SI: v_or_b32_e32
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; VI-DAG: v_cvt_f32_u32_e32
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; VI-DAG: v_cvt_f32_u32_e32
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; VI-DAG: v_cvt_f16_f32_e32
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; VI-DAG: v_cvt_f16_f32_sdwa
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; VI: v_or_b32_e32
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @uitofp_v2i32_to_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x i32> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a
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%r.val = uitofp <2 x i32> %a.val to <2 x half>
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f16:
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; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
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; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
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; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
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; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[R_CMP]]
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; GCN-NEXT: v_cvt_f16_f32_e32 [[R_F16:v[0-9]+]], [[RESULT]]
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; GCN: buffer_store_short
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; GCN: s_endpgm
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define amdgpu_kernel void @s_uint_to_fp_i1_to_f16(half addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float, float addrspace(1) * %in0
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%b = load float, float addrspace(1) * %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 1.000000e+00
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%result = xor i1 %acmp, %bcmp
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%fp = uitofp i1 %result to half
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store half %fp, half addrspace(1)* %out
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ret void
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}
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; f16 = uitofp i64 is in uint_to_fp.i64.ll
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