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812ee5bc7c
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
56 lines
1.4 KiB
LLVM
56 lines
1.4 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
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define i32 @t1(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t1
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%add.ptr = getelementptr inbounds i32* %ptr, i32 1
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%0 = load i32* %add.ptr, align 4
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; ARM: ldr r{{[0-9]}}, [r0, #4]
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ret i32 %0
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}
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define i32 @t2(i32* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t2
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%add.ptr = getelementptr inbounds i32* %ptr, i32 63
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%0 = load i32* %add.ptr, align 4
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; ARM: ldr.w r{{[0-9]}}, [r0, #252]
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ret i32 %0
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}
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define zeroext i16 @t3(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t3
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%add.ptr = getelementptr inbounds i16* %ptr, i16 1
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%0 = load i16* %add.ptr, align 4
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; ARM: ldrh r{{[0-9]}}, [r0, #2]
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ret i16 %0
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}
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define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t4
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%add.ptr = getelementptr inbounds i16* %ptr, i16 63
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%0 = load i16* %add.ptr, align 4
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; ARM: ldrh.w r{{[0-9]}}, [r0, #126]
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ret i16 %0
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}
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define zeroext i8 @t5(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t5
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%add.ptr = getelementptr inbounds i8* %ptr, i8 1
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%0 = load i8* %add.ptr, align 4
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; ARM: ldrb r{{[0-9]}}, [r0, #1]
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ret i8 %0
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}
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define zeroext i8 @t6(i8* nocapture %ptr) nounwind readonly {
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entry:
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; ARM: t6
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%add.ptr = getelementptr inbounds i8* %ptr, i8 63
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%0 = load i8* %add.ptr, align 4
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; ARM: ldrb.w r{{[0-9]}}, [r0, #63]
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ret i8 %0
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}
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