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0b6ea5de72
Some of the SHA instructions take a scalar i32 as one argument (largely because they work on 160-bit hash fragments). This wasn't reflected in the IR previously, with ARM and AArch64 choosing different types (<4 x i32> and <1 x i32> respectively) which was ugly. This makes all the affected intrinsics take a uniform "i32", allowing them to become non-polymorphic at the same time. llvm-svn: 200706
60 lines
3.3 KiB
LLVM
60 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) {
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%tmp = load <16 x i8>* %a
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%tmp2 = load <16 x i8>* %b
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%tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2)
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; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2)
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; CHECK: aese.8 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4)
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; CHECK: aesimc.8 q{{[0-9]+}}, q{{[0-9]+}}
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%tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5)
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; CHECK: aesmc.8 q{{[0-9]+}}, q{{[0-9]+}}
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ret <16 x i8> %tmp6
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}
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define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) {
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%tmp = load <4 x i32>* %a
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%tmp2 = load <4 x i32>* %b
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%tmp3 = load <4 x i32>* %c
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%scalar = extractelement <4 x i32> %tmp, i32 0
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%resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar)
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%res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0
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; CHECK: sha1h.32 q{{[0-9]+}}, q{{[0-9]+}}
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%res2 = call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %tmp2, i32 %scalar, <4 x i32> %res1)
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; CHECK: sha1c.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res3 = call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %res2, i32 %scalar, <4 x i32> %res1)
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; CHECK: sha1m.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res4 = call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %res3, i32 %scalar, <4 x i32> %res1)
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; CHECK: sha1p.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1)
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; CHECK: sha1su0.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1)
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; CHECK: sha1su1.32 q{{[0-9]+}}, q{{[0-9]+}}
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%res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1)
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; CHECK: sha256h.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
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; CHECK: sha256h2.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
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; CHECK: sha256su1.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
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%res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
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; CHECK: sha256su0.32 q{{[0-9]+}}, q{{[0-9]+}}
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ret <4 x i32> %res10
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}
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declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>)
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declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>)
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declare i32 @llvm.arm.neon.sha1h(i32)
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declare <4 x i32> @llvm.arm.neon.sha1c(<4 x i32>, i32, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha1m(<4 x i32>, i32, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha1p(<4 x i32>, i32, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha256h(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32>, <4 x i32>)
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