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7f8ca02cf4
ARM v7M has ldrex/strex but not ldrexd/strexd. This means 32-bit operations should work as normal, but 64-bit ones are almost certainly doomed. Patch by Phoebe Buckheister. llvm-svn: 211042
60 lines
1.1 KiB
LLVM
60 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s
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; CHECK-LABEL: f0:
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; CHECK-NOT: ldrexd
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define i64 @f0(i64* %p) nounwind readonly {
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entry:
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%0 = load atomic i64* %p seq_cst, align 8
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ret i64 %0
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}
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; CHECK-LABEL: f1:
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; CHECK-NOT: strexd
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define void @f1(i64* %p) nounwind readonly {
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entry:
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store atomic i64 0, i64* %p seq_cst, align 8
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ret void
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}
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; CHECK-LABEL: f2:
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; CHECK-NOT: ldrexd
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; CHECK-NOT: strexd
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define i64 @f2(i64* %p) nounwind readonly {
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entry:
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%0 = atomicrmw add i64* %p, i64 1 seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: f3:
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; CHECK: ldr
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define i32 @f3(i32* %p) nounwind readonly {
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entry:
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%0 = load atomic i32* %p seq_cst, align 4
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ret i32 %0
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}
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; CHECK-LABEL: f4:
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; CHECK: ldrb
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define i8 @f4(i8* %p) nounwind readonly {
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entry:
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%0 = load atomic i8* %p seq_cst, align 4
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ret i8 %0
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}
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; CHECK-LABEL: f5:
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; CHECK: str
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define void @f5(i32* %p) nounwind readonly {
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entry:
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store atomic i32 0, i32* %p seq_cst, align 4
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ret void
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}
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; CHECK-LABEL: f6:
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; CHECK: ldrex
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; CHECK: strex
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define i32 @f6(i32* %p) nounwind readonly {
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entry:
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%0 = atomicrmw add i32* %p, i32 1 seq_cst
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ret i32 %0
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}
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