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2cb9c461b4
Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
61 lines
2.1 KiB
LLVM
61 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
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; RUN: llc < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
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define double @func0(double %d0, double %d1) nounwind readnone {
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entry:
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;
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f1
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mthc1 $[[INS]], $f0
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63
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; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1
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; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 64: dmtc1 $[[OR]], $f0
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; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
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; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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%call = tail call double @copysign(double %d0, double %d1) nounwind readnone
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ret double %call
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}
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declare double @copysign(double, double) nounwind readnone
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define float @func1(float %f0, float %f1) nounwind readnone {
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entry:
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; 32: lui $[[MSK1:[0-9]+]], 32768
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; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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; 32: mtc1 $[[OR]], $f0
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; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1
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; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
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; 32R2: mtc1 $[[INS]], $f0
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%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
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ret float %call
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}
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declare float @copysignf(float, float) nounwind readnone
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