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llvm-mirror/test/CodeGen/Mips/rotate.ll
Simon Atanasyan 226923909e [Mips] Adjust float ABI settings in case of MIPS16 mode.
Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).

The patch reviewed by Reed Kotler.

llvm-svn: 195123
2013-11-19 12:20:17 +00:00

46 lines
1009 B
LLVM

; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16
; CHECK: rotrv $2, $4
; mips16: .ent rot0
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b
%sub = sub i32 32, %b
%shr = lshr i32 %a, %sub
%or = or i32 %shr, %shl
ret i32 %or
}
; CHECK: rotr $2, $4, 22
; mips16: .ent rot1
define i32 @rot1(i32 %a) nounwind readnone {
entry:
%shl = shl i32 %a, 10
%shr = lshr i32 %a, 22
%or = or i32 %shl, %shr
ret i32 %or
}
; CHECK: rotrv $2, $4, $5
; mips16: .ent rot2
define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
entry:
%shr = lshr i32 %a, %b
%sub = sub i32 32, %b
%shl = shl i32 %a, %sub
%or = or i32 %shl, %shr
ret i32 %or
}
; CHECK: rotr $2, $4, 10
; mips16: .ent rot3
define i32 @rot3(i32 %a) nounwind readnone {
entry:
%shr = lshr i32 %a, 10
%shl = shl i32 %a, 22
%or = or i32 %shr, %shl
ret i32 %or
}