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477ae4e17b
Summary: This is found during review of https://reviews.llvm.org/D67088. CHECK-DAG is non-overlapping after https://reviews.llvm.org/D47106. -allow-deprecated-dag-overlap was introduced to temporary accept old behavior. But it actually hide some broken tests, eg: `test/CodeGen/PowerPC/swaps-le-1.ll` The codegen has changed, but the CHECK-DAG still PASS due to allowing `overlap`. This patch remove the deprecated options, and fix the broken tests. Reviewers: #powerpc, hfinkel, nemanjai, steven.zhang, shchenz Reviewed By: shchenz Subscribers: shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69733
114 lines
2.6 KiB
LLVM
114 lines
2.6 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR7
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR8
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; RUN: llc -verify-machineinstrs -mcpu=a2q < %s | FileCheck %s -check-prefix=A2Q
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define void @foo1(double* nocapture %x, double* nocapture readonly %y) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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%1 = bitcast double* %y to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %0, i8* align 8 %1, i64 32, i1 false)
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ret void
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; PWR7-LABEL: @foo1
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; PWR7-NOT: bl memcpy
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; PWR7-DAG: li [[OFFSET:[0-9]+]], 16
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; PWR7-DAG: lxvd2x [[TMP0:[0-9]+]], 4, [[OFFSET]]
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; PWR7-DAG: stxvd2x [[TMP0]], 3, [[OFFSET]]
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; PWR7-DAG: lxvd2x [[TMP1:[0-9]+]], 0, 4
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; PWR7-DAG: stxvd2x [[TMP1]], 0, 3
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; PWR7: blr
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; PWR8-LABEL: @foo1
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; PWR8: lxvw4x
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @foo1
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; A2Q-NOT: bl memcpy
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; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #0
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; Function Attrs: nounwind
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define void @foo2(double* nocapture %x, double* nocapture readonly %y) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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%1 = bitcast double* %y to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %0, i8* align 8 %1, i64 128, i1 false)
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ret void
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; PWR7-LABEL: @foo2
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; PWR7: bl memcpy
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; PWR7: blr
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; PWR8-LABEL: @foo2
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; PWR8: lxvw4x
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @foo2
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; A2Q-NOT: bl memcpy
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; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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define void @bar1(double* nocapture %x) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 128, i1 false)
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ret void
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; PWR7-LABEL: @bar1
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; PWR7-NOT: bl memset
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; PWR7: stxvw4x
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; PWR7: blr
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; PWR8-LABEL: @bar1
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; PWR8-NOT: bl memset
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @bar1
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; A2Q-NOT: bl memset
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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define void @bar2(double* nocapture %x) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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tail call void @llvm.memset.p0i8.i64(i8* align 32 %0, i8 0, i64 128, i1 false)
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ret void
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; PWR7-LABEL: @bar2
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; PWR7-NOT: bl memset
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; PWR7: stxvw4x
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; PWR7: blr
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; PWR8-LABEL: @bar2
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; PWR8-NOT: bl memset
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @bar2
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; A2Q-NOT: bl memset
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; A2Q: qvstfdx
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; A2Q: blr
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}
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; Function Attrs: nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #0
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attributes #0 = { nounwind }
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