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a619e90821
The instruction addi is usually used to post increase the loop indvar, which looks like this: label_X: load x, base(i) ... y = op x ... i = addi i, 1 goto label_X However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1, it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve. Reviewed By: jji Differential Revision: https://reviews.llvm.org/D80269
65 lines
1.9 KiB
LLVM
65 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
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; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
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define void @main() nounwind #0 {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: bl strtol
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: bl calloc
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; CHECK-NEXT: nop
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; CHECK-NEXT: li 5, 0
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; CHECK-NEXT: addi 3, 3, -4
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; CHECK-NEXT: li 6, 1
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; CHECK-NEXT: clrldi 4, 30, 32
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; CHECK-NEXT: mtctr 4
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; CHECK-NEXT: mullw 4, 5, 5
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; CHECK-NEXT: bdz .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: addi 5, 6, 1
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: mullw 4, 6, 6
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; CHECK-NEXT: bdz .LBB0_3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: mullw 4, 5, 5
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; CHECK-NEXT: addi 5, 5, 1
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: stwu 4, 4(3)
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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%1 = tail call i64 @strtol()
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%2 = trunc i64 %1 to i32
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%3 = tail call noalias i8* @calloc()
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%4 = bitcast i8* %3 to i32*
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%5 = zext i32 %2 to i64
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br label %6
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6: ; preds = %6, %0
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%7 = phi i64 [ %11, %6 ], [ 0, %0 ]
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%8 = trunc i64 %7 to i32
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%9 = mul nsw i32 %8, %8
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%10 = getelementptr inbounds i32, i32* %4, i64 %7
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store i32 %9, i32* %10, align 4
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%11 = add nuw nsw i64 %7, 1
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%12 = icmp eq i64 %11, %5
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br i1 %12, label %13, label %6
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13: ; preds = %6
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ret void
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}
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declare i8* @calloc() local_unnamed_addr
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declare i64 @strtol() local_unnamed_addr
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