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71c5d5fa5f
In the case where op = add, y = base_ptr, and x = offset, this transform: (op y, (op x, c1)) -> (op (op x, y), c1) breaks the canonical form of add by putting the base pointer in the second operand and the offset in the first. This fix is important for the R600 target, because for some address spaces the base pointer and the offset are stored in separate register classes. The old pattern caused the ISel code for matching addressing modes to put the base pointer and offset in the wrong register classes, which required no-trivial code transformations to fix. llvm-svn: 262148
164 lines
5.8 KiB
LLVM
164 lines
5.8 KiB
LLVM
; RUN: llc < %s -mattr=sse2 -mtriple=i386-unknown-linux-gnu | FileCheck %s
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; Source file looks something like this:
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;
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; typedef int AAA[100][100];
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;
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; void testCombineMultiplies(AAA a,int lll)
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; {
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; int LOC = lll + 5;
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;
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; a[LOC][LOC] = 11;
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;
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; a[LOC][20] = 22;
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; a[LOC+20][20] = 33;
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; }
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;
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; We want to make sure we don't generate 2 multiply instructions,
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; one for a[LOC][] and one for a[LOC+20]. visitMUL in DAGCombiner.cpp
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; should combine the instructions in such a way to avoid the extra
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; multiply.
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;
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; Output looks roughly like this:
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;
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; movl 8(%esp), %eax
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; movl 12(%esp), %ecx
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; imull $400, %ecx, %edx # imm = 0x190
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; leal (%edx,%eax), %esi
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; movl $11, 2020(%esi,%ecx,4)
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; movl $22, 2080(%edx,%eax)
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; movl $33, 10080(%edx,%eax)
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;
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; CHECK-LABEL: testCombineMultiplies
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; CHECK: imull $400, [[ARG1:%[a-z]+]], [[MUL:%[a-z]+]] # imm = 0x190
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; CHECK-NEXT: leal ([[ARG2:%[a-z]+]],[[MUL]]), [[LEA:%[a-z]+]]
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; CHECK-NEXT: movl $11, {{[0-9]+}}([[LEA]],[[ARG1]],4)
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; CHECK-NEXT: movl $22, {{[0-9]+}}([[ARG2]],[[MUL]])
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; CHECK-NEXT: movl $33, {{[0-9]+}}([[ARG2]],[[MUL]])
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; CHECK: retl
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;
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; Function Attrs: nounwind
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define void @testCombineMultiplies([100 x i32]* nocapture %a, i32 %lll) {
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entry:
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%add = add nsw i32 %lll, 5
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%arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32]* %a, i32 %add, i32 %add
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store i32 11, i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds [100 x i32], [100 x i32]* %a, i32 %add, i32 20
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store i32 22, i32* %arrayidx3, align 4
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%add4 = add nsw i32 %lll, 25
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%arrayidx6 = getelementptr inbounds [100 x i32], [100 x i32]* %a, i32 %add4, i32 20
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store i32 33, i32* %arrayidx6, align 4
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ret void
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}
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; Test for the same optimization on vector multiplies.
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;
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; Source looks something like this:
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;
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; typedef int v4int __attribute__((__vector_size__(16)));
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;
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; v4int x;
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; v4int v2, v3;
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; void testCombineMultiplies_splat(v4int v1) {
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; v2 = (v1 + (v4int){ 11, 11, 11, 11 }) * (v4int) {22, 22, 22, 22};
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; v3 = (v1 + (v4int){ 33, 33, 33, 33 }) * (v4int) {22, 22, 22, 22};
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; x = (v1 + (v4int){ 11, 11, 11, 11 });
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; }
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;
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; Output looks something like this:
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;
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; testCombineMultiplies_splat: # @testCombineMultiplies_splat
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; # BB#0: # %entry
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; movdqa .LCPI1_0, %xmm1 # xmm1 = [11,11,11,11]
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; paddd %xmm0, %xmm1
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; movdqa .LCPI1_1, %xmm2 # xmm2 = [22,22,22,22]
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; pshufd $245, %xmm0, %xmm3 # xmm3 = xmm0[1,1,3,3]
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; pmuludq %xmm2, %xmm0
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; pshufd $232, %xmm0, %xmm0 # xmm0 = xmm0[0,2,2,3]
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; pmuludq %xmm2, %xmm3
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; pshufd $232, %xmm3, %xmm2 # xmm2 = xmm3[0,2,2,3]
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; punpckldq %xmm2, %xmm0 # xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; movdqa .LCPI1_2, %xmm2 # xmm2 = [242,242,242,242]
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; paddd %xmm0, %xmm2
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; paddd .LCPI1_3, %xmm0
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; movdqa %xmm2, v2
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; movdqa %xmm0, v3
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; movdqa %xmm1, x
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; retl
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;
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; Again, we want to make sure we don't generate two different multiplies.
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; We should have a single multiply for "v1 * {22, 22, 22, 22}" (made up of two
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; pmuludq instructions), followed by two adds. Without this optimization, we'd
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; do 2 adds, followed by 2 multiplies (i.e. 4 pmuludq instructions).
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;
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; CHECK-LABEL: testCombineMultiplies_splat
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; CHECK: movdqa .LCPI1_0, [[C11:%xmm[0-9]]]
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; CHECK-NEXT: paddd %xmm0, [[C11]]
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; CHECK-NEXT: movdqa .LCPI1_1, [[C22:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $245, %xmm0, [[T1:%xmm[0-9]]]
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; CHECK-NEXT: pmuludq [[C22]], [[T2:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $232, [[T2]], [[T3:%xmm[0-9]]]
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; CHECK-NEXT: pmuludq [[C22]], [[T4:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $232, [[T4]], [[T5:%xmm[0-9]]]
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; CHECK-NEXT: punpckldq [[T5]], [[T6:%xmm[0-9]]]
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; CHECK-NEXT: movdqa .LCPI1_2, [[C242:%xmm[0-9]]]
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; CHECK-NEXT: paddd [[T6]], [[C242]]
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; CHECK-NEXT: paddd .LCPI1_3, [[C726:%xmm[0-9]]]
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; CHECK-NEXT: movdqa [[C242]], v2
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; CHECK-NEXT: [[C726]], v3
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; CHECK-NEXT: [[C11]], x
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; CHECK-NEXT: retl
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@v2 = common global <4 x i32> zeroinitializer, align 16
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@v3 = common global <4 x i32> zeroinitializer, align 16
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@x = common global <4 x i32> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @testCombineMultiplies_splat(<4 x i32> %v1) {
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entry:
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%add1 = add <4 x i32> %v1, <i32 11, i32 11, i32 11, i32 11>
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%mul1 = mul <4 x i32> %add1, <i32 22, i32 22, i32 22, i32 22>
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%add2 = add <4 x i32> %v1, <i32 33, i32 33, i32 33, i32 33>
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%mul2 = mul <4 x i32> %add2, <i32 22, i32 22, i32 22, i32 22>
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store <4 x i32> %mul1, <4 x i32>* @v2, align 16
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store <4 x i32> %mul2, <4 x i32>* @v3, align 16
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store <4 x i32> %add1, <4 x i32>* @x, align 16
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ret void
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}
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; Finally, check the non-splatted vector case. This is very similar
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; to the previous test case, except for the vector values.
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;
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; CHECK-LABEL: testCombineMultiplies_non_splat
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; CHECK: movdqa .LCPI2_0, [[C11:%xmm[0-9]]]
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; CHECK-NEXT: paddd %xmm0, [[C11]]
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; CHECK-NEXT: movdqa .LCPI2_1, [[C22:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $245, %xmm0, [[T1:%xmm[0-9]]]
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; CHECK-NEXT: pmuludq [[C22]], [[T2:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $232, [[T2]], [[T3:%xmm[0-9]]]
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; CHECK-NEXT: pshufd $245, [[C22]], [[T7:%xmm[0-9]]]
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; CHECK-NEXT: pmuludq [[T1]], [[T7]]
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; CHECK-NEXT: pshufd $232, [[T7]], [[T5:%xmm[0-9]]]
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; CHECK-NEXT: punpckldq [[T5]], [[T6:%xmm[0-9]]]
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; CHECK-NEXT: movdqa .LCPI2_2, [[C242:%xmm[0-9]]]
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; CHECK-NEXT: paddd [[T6]], [[C242]]
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; CHECK-NEXT: paddd .LCPI2_3, [[C726:%xmm[0-9]]]
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; CHECK-NEXT: movdqa [[C242]], v2
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; CHECK-NEXT: [[C726]], v3
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; CHECK-NEXT: [[C11]], x
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; CHECK-NEXT: retl
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; Function Attrs: nounwind
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define void @testCombineMultiplies_non_splat(<4 x i32> %v1) {
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entry:
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%add1 = add <4 x i32> %v1, <i32 11, i32 22, i32 33, i32 44>
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%mul1 = mul <4 x i32> %add1, <i32 22, i32 33, i32 44, i32 55>
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%add2 = add <4 x i32> %v1, <i32 33, i32 44, i32 55, i32 66>
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%mul2 = mul <4 x i32> %add2, <i32 22, i32 33, i32 44, i32 55>
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store <4 x i32> %mul1, <4 x i32>* @v2, align 16
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store <4 x i32> %mul2, <4 x i32>* @v3, align 16
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store <4 x i32> %add1, <4 x i32>* @x, align 16
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ret void
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}
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