mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 20:12:56 +02:00
f0ca422f64
autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
374 lines
10 KiB
LLVM
374 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s
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; SSE2 Logical Shift Left
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define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sllw_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sllw_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: paddw %xmm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sllw_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psllw $15, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <8 x i16> %shl
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}
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define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
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; CHECK-LABEL: test_slld_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
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; CHECK-LABEL: test_slld_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: paddd %xmm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
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; CHECK-LABEL: test_slld_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pslld $31, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
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ret <4 x i32> %shl
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}
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define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
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; CHECK-LABEL: test_sllq_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = shl <2 x i64> %InVec, <i64 0, i64 0>
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ret <2 x i64> %shl
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}
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define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
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; CHECK-LABEL: test_sllq_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: paddq %xmm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <2 x i64> %InVec, <i64 1, i64 1>
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ret <2 x i64> %shl
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}
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define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
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; CHECK-LABEL: test_sllq_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psllq $63, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = shl <2 x i64> %InVec, <i64 63, i64 63>
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ret <2 x i64> %shl
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}
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; SSE2 Arithmetic Shift
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define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sraw_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sraw_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psraw $1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
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; CHECK-LABEL: test_sraw_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psraw $15, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <8 x i16> %shl
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}
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define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srad_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srad_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrad $1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srad_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrad $31, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
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ret <4 x i32> %shl
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}
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; SSE Logical Shift Right
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define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
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; CHECK-LABEL: test_srlw_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
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; CHECK-LABEL: test_srlw_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrlw $1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
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; CHECK-LABEL: test_srlw_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrlw $15, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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ret <8 x i16> %shl
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}
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define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srld_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srld_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrld $1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
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; CHECK-LABEL: test_srld_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrld $31, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
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ret <4 x i32> %shl
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}
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define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
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; CHECK-LABEL: test_srlq_1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
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ret <2 x i64> %shl
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}
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define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
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; CHECK-LABEL: test_srlq_2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrlq $1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
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ret <2 x i64> %shl
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}
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define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
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; CHECK-LABEL: test_srlq_3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: psrlq $63, %xmm0
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; CHECK-NEXT: retq
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entry:
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%shl = lshr <2 x i64> %InVec, <i64 63, i64 63>
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ret <2 x i64> %shl
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}
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define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: sra_sra_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrad $6, %xmm0
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; CHECK-NEXT: retq
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%sra0 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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%sra1 = ashr <4 x i32> %sra0, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %sra1
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}
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define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: srl_srl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrld $6, %xmm0
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; CHECK-NEXT: retq
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%srl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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%srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %srl1
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}
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define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: srl_shl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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%srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %srl1
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}
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define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: srl_sra_31_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrld $31, %xmm0
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; CHECK-NEXT: retq
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%sra = ashr <4 x i32> %x, %y
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%srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31>
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ret <4 x i32> %srl1
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}
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define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: shl_shl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: pslld $6, %xmm0
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; CHECK-NEXT: retq
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%shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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%shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %shl1
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}
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define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: shl_sra_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%shl0 = ashr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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%shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %shl1
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}
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define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: shl_srl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: pslld $3, %xmm0
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%shl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
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%shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
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ret <4 x i32> %shl1
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}
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define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind {
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; CHECK-LABEL: shl_zext_srl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%srl = lshr <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
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%zext = zext <4 x i16> %srl to <4 x i32>
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%shl = shl <4 x i32> %zext, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %shl
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}
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define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: sra_trunc_srl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrad $19, %xmm0
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; CHECK-NEXT: retq
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%srl = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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%trunc = trunc <4 x i32> %srl to <4 x i16>
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%sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3>
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ret <4 x i16> %sra
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}
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define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind {
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; CHECK-LABEL: shl_zext_shl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
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; CHECK-NEXT: pslld $19, %xmm0
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; CHECK-NEXT: retq
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%shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
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%ext = zext <4 x i16> %shl0 to <4 x i32>
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%shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
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ret <4 x i32> %shl1
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}
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define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: sra_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrad $3, %xmm0
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; CHECK-NEXT: retq
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%sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %sra
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}
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define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: srl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: psrld $3, %xmm0
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; CHECK-NEXT: retq
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%sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %sra
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}
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define <4 x i32> @shl_v4i32(<4 x i32> %x) nounwind {
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; CHECK-LABEL: shl_v4i32:
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; CHECK: # BB#0:
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; CHECK-NEXT: pslld $3, %xmm0
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; CHECK-NEXT: retq
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%sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %sra
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}
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