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https://github.com/RPCS3/llvm-mirror.git
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730af75e9f
Reinteroduce the code for moving ARGUMENTS back to the top of the basic block. While the ARGUMENTS physical register prevents sinking and scheduling from moving them, it does not appear to be sufficient to prevent SelectionDAG from moving them down in the initial schedule. This patch introduces a patch that moves them back to the top immediately after SelectionDAG runs. This is still hopefully a temporary solution. http://reviews.llvm.org/D14750 is one alternative, though the review has not been favorable, and proposed alternatives are longer-term and have other downsides. This fixes the main outstanding -verify-machineinstrs failures, so it adds -verify-machineinstrs to several tests. Differential Revision: http://reviews.llvm.org/D15377 llvm-svn: 255125
175 lines
5.0 KiB
LLVM
175 lines
5.0 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -disable-block-placement -verify-machineinstrs | FileCheck %s
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; Test switch instructions. Block placement is disabled because it reorders
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; the blocks in a way that isn't interesting here.
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target datalayout = "e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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declare void @foo0()
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declare void @foo1()
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declare void @foo2()
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declare void @foo3()
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declare void @foo4()
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declare void @foo5()
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; CHECK-LABEL: bar32:
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; CHECK: block BB0_8{{$}}
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; CHECK: block BB0_7{{$}}
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; CHECK: block BB0_6{{$}}
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; CHECK: block BB0_5{{$}}
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; CHECK: block BB0_4{{$}}
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; CHECK: block BB0_3{{$}}
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; CHECK: block BB0_2{{$}}
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; CHECK: tableswitch {{[^,]*}}, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_5, BB0_6, BB0_7{{$}}
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; CHECK: BB0_2:
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; CHECK: call foo0
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; CHECK: BB0_3:
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; CHECK: call foo1
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; CHECK: BB0_4:
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; CHECK: call foo2
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; CHECK: BB0_5:
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; CHECK: call foo3
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; CHECK: BB0_6:
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; CHECK: call foo4
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; CHECK: BB0_7:
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; CHECK: call foo5
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; CHECK: BB0_8:
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; CHECK: return{{$}}
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define void @bar32(i32 %n) {
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entry:
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switch i32 %n, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb
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i32 2, label %sw.bb
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i32 3, label %sw.bb
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i32 4, label %sw.bb
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i32 5, label %sw.bb
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i32 6, label %sw.bb
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i32 7, label %sw.bb.1
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i32 8, label %sw.bb.1
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i32 9, label %sw.bb.1
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i32 10, label %sw.bb.1
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i32 11, label %sw.bb.1
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i32 12, label %sw.bb.1
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i32 13, label %sw.bb.1
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i32 14, label %sw.bb.1
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i32 15, label %sw.bb.2
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i32 16, label %sw.bb.2
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i32 17, label %sw.bb.2
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i32 18, label %sw.bb.2
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i32 19, label %sw.bb.2
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i32 20, label %sw.bb.2
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i32 21, label %sw.bb.3
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i32 22, label %sw.bb.4
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i32 23, label %sw.bb.5
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo0()
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br label %sw.epilog
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sw.bb.1: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo1()
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br label %sw.epilog
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sw.bb.2: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo2()
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br label %sw.epilog
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sw.bb.3: ; preds = %entry
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tail call void @foo3()
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br label %sw.epilog
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sw.bb.4: ; preds = %entry
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tail call void @foo4()
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br label %sw.epilog
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sw.bb.5: ; preds = %entry
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tail call void @foo5()
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %sw.bb.2, %sw.bb.1, %sw.bb
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ret void
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}
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; CHECK-LABEL: bar64:
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; CHECK: block BB1_8{{$}}
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; CHECK: block BB1_7{{$}}
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; CHECK: block BB1_6{{$}}
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; CHECK: block BB1_5{{$}}
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; CHECK: block BB1_4{{$}}
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; CHECK: block BB1_3{{$}}
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; CHECK: block BB1_2{{$}}
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; CHECK: tableswitch {{[^,]*}}, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_5, BB1_6, BB1_7{{$}}
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; CHECK: BB1_2:
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; CHECK: call foo0
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; CHECK: BB1_3:
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; CHECK: call foo1
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; CHECK: BB1_4:
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; CHECK: call foo2
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; CHECK: BB1_5:
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; CHECK: call foo3
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; CHECK: BB1_6:
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; CHECK: call foo4
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; CHECK: BB1_7:
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; CHECK: call foo5
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; CHECK: BB1_8:
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; CHECK: return{{$}}
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define void @bar64(i64 %n) {
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entry:
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switch i64 %n, label %sw.epilog [
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i64 0, label %sw.bb
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i64 1, label %sw.bb
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i64 2, label %sw.bb
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i64 3, label %sw.bb
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i64 4, label %sw.bb
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i64 5, label %sw.bb
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i64 6, label %sw.bb
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i64 7, label %sw.bb.1
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i64 8, label %sw.bb.1
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i64 9, label %sw.bb.1
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i64 10, label %sw.bb.1
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i64 11, label %sw.bb.1
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i64 12, label %sw.bb.1
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i64 13, label %sw.bb.1
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i64 14, label %sw.bb.1
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i64 15, label %sw.bb.2
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i64 16, label %sw.bb.2
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i64 17, label %sw.bb.2
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i64 18, label %sw.bb.2
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i64 19, label %sw.bb.2
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i64 20, label %sw.bb.2
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i64 21, label %sw.bb.3
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i64 22, label %sw.bb.4
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i64 23, label %sw.bb.5
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo0()
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br label %sw.epilog
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sw.bb.1: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo1()
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br label %sw.epilog
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sw.bb.2: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
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tail call void @foo2()
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br label %sw.epilog
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sw.bb.3: ; preds = %entry
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tail call void @foo3()
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br label %sw.epilog
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sw.bb.4: ; preds = %entry
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tail call void @foo4()
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br label %sw.epilog
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sw.bb.5: ; preds = %entry
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tail call void @foo5()
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %sw.bb.2, %sw.bb.1, %sw.bb
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ret void
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}
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