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https://github.com/RPCS3/llvm-mirror.git
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c23de517a6
On AVX and AVX2, BROADCAST instructions can load a scalar into all elements of a target vector. This patch improves the lowering of 'splat' shuffles of a loaded vector into a broadcast - currently the lowering only works for cases where we are splatting the zero'th element, which is now generalised to any element. Fix for PR23022 Differential Revision: http://reviews.llvm.org/D15310 llvm-svn: 255061
378 lines
14 KiB
LLVM
378 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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define <4 x i64> @A(i64* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: A:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd (%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%q = load i64, i64* %ptr, align 8
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%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
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%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
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%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
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ret <4 x i64> %vecinit6.i
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}
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define <8 x i32> @B(i32* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: B:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%q = load i32, i32* %ptr, align 4
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%vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
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%vecinit2.i = insertelement <8 x i32> %vecinit.i, i32 %q, i32 1
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%vecinit4.i = insertelement <8 x i32> %vecinit2.i, i32 %q, i32 2
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%vecinit6.i = insertelement <8 x i32> %vecinit4.i, i32 %q, i32 3
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ret <8 x i32> %vecinit6.i
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}
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define <4 x double> @C(double* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: C:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd (%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%q = load double, double* %ptr, align 8
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%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
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%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
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%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
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%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
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ret <4 x double> %vecinit6.i
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}
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define <8 x float> @D(float* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: D:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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%vecinit.i = insertelement <8 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <8 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <8 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <8 x float> %vecinit4.i, float %q, i32 3
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ret <8 x float> %vecinit6.i
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}
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;;;; 128-bit versions
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define <4 x float> @e(float* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: e:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %xmm0
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; CHECK-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
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ret <4 x float> %vecinit6.i
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}
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; Don't broadcast constants on pre-AVX2 hardware.
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define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: _e2:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [-7.812500e-03,-7.812500e-03,-7.812500e-03,-7.812500e-03]
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; CHECK-NEXT: retq
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entry:
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%vecinit.i = insertelement <4 x float> undef, float 0xbf80000000000000, i32 0
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%vecinit2.i = insertelement <4 x float> %vecinit.i, float 0xbf80000000000000, i32 1
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%vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
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%vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
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ret <4 x float> %vecinit6.i
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}
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define <4 x i32> @F(i32* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: F:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %xmm0
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; CHECK-NEXT: retq
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entry:
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%q = load i32, i32* %ptr, align 4
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%vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
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%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %q, i32 1
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%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %q, i32 2
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%vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %q, i32 3
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ret <4 x i32> %vecinit6.i
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}
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; FIXME: Pointer adjusted broadcasts
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define <4 x i32> @load_splat_4i32_4i32_1111(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4i32_4i32_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = mem[1,1,1,1]
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x i32>, <4 x i32>* %ptr
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%ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %ret
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}
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define <8 x i32> @load_splat_8i32_4i32_33333333(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_8i32_4i32_33333333:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = mem[3,3,3,3]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x i32>, <4 x i32>* %ptr
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%ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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ret <8 x i32> %ret
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}
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define <8 x i32> @load_splat_8i32_8i32_55555555(<8 x i32>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_8i32_8i32_55555555:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps (%rdi), %ymm0
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <8 x i32>, <8 x i32>* %ptr
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%ret = shufflevector <8 x i32> %ld, <8 x i32> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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ret <8 x i32> %ret
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}
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define <4 x float> @load_splat_4f32_4f32_1111(<4 x float>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4f32_4f32_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss 4(%rdi), %xmm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x float>, <4 x float>* %ptr
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%ret = shufflevector <4 x float> %ld, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x float> %ret
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}
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define <8 x float> @load_splat_8f32_4f32_33333333(<4 x float>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_8f32_4f32_33333333:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss 12(%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x float>, <4 x float>* %ptr
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%ret = shufflevector <4 x float> %ld, <4 x float> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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ret <8 x float> %ret
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}
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define <8 x float> @load_splat_8f32_8f32_55555555(<8 x float>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_8f32_8f32_55555555:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss 20(%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <8 x float>, <8 x float>* %ptr
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%ret = shufflevector <8 x float> %ld, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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ret <8 x float> %ret
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}
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define <2 x i64> @load_splat_2i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_2i64_2i64_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
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; CHECK-NEXT: retq
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entry:
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%ld = load <2 x i64>, <2 x i64>* %ptr
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%ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %ret
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}
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define <4 x i64> @load_splat_4i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4i64_2i64_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <2 x i64>, <2 x i64>* %ptr
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%ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i64> %ret
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}
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define <4 x i64> @load_splat_4i64_4i64_2222(<4 x i64>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4i64_4i64_2222:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovapd (%rdi), %ymm0
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x i64>, <4 x i64>* %ptr
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%ret = shufflevector <4 x i64> %ld, <4 x i64> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i64> %ret
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}
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define <2 x double> @load_splat_2f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_2f64_2f64_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
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; CHECK-NEXT: retq
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entry:
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%ld = load <2 x double>, <2 x double>* %ptr
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%ret = shufflevector <2 x double> %ld, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %ret
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}
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define <4 x double> @load_splat_4f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4f64_2f64_1111:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd 8(%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <2 x double>, <2 x double>* %ptr
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%ret = shufflevector <2 x double> %ld, <2 x double> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x double> %ret
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}
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define <4 x double> @load_splat_4f64_4f64_2222(<4 x double>* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: load_splat_4f64_4f64_2222:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastsd 16(%rdi), %ymm0
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; CHECK-NEXT: retq
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entry:
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%ld = load <4 x double>, <4 x double>* %ptr
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%ret = shufflevector <4 x double> %ld, <4 x double> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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ret <4 x double> %ret
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}
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; Unsupported vbroadcasts
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define <2 x i64> @G(i64* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: G:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; CHECK-NEXT: retq
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entry:
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%q = load i64, i64* %ptr, align 8
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%vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <2 x i64> %vecinit.i, i64 %q, i32 1
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ret <2 x i64> %vecinit2.i
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}
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define <4 x i32> @H(<4 x i32> %a) {
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; CHECK-LABEL: H:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; CHECK-NEXT: retq
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entry:
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%x = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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ret <4 x i32> %x
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}
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define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
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; CHECK-LABEL: I:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
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; CHECK-NEXT: retq
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entry:
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%q = load double, double* %ptr, align 4
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%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
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%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
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ret <2 x double> %vecinit2.i
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}
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define <4 x float> @_RR(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
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; CHECK-LABEL: _RR:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %xmm0
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; CHECK-NEXT: movl (%rsi), %eax
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; CHECK-NEXT: movl %eax, (%rax)
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; CHECK-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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%vecinit.i = insertelement <4 x float> undef, float %q, i32 0
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%vecinit2.i = insertelement <4 x float> %vecinit.i, float %q, i32 1
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%vecinit4.i = insertelement <4 x float> %vecinit2.i, float %q, i32 2
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%vecinit6.i = insertelement <4 x float> %vecinit4.i, float %q, i32 3
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; force a chain
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%j = load i32, i32* %k, align 4
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store i32 %j, i32* undef
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ret <4 x float> %vecinit6.i
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}
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define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp {
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; CHECK-LABEL: _RR2:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: vbroadcastss (%rdi), %xmm0
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; CHECK-NEXT: retq
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entry:
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%q = load float, float* %ptr, align 4
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%v = insertelement <4 x float> undef, float %q, i32 0
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%t = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %t
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}
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; These tests check that a vbroadcast instruction is used when we have a splat
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; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
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; (via the insertelements).
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define <8 x float> @splat_concat1(float* %p) {
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; CHECK-LABEL: splat_concat1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss (%rdi), %ymm0
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; CHECK-NEXT: retq
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%1 = load float, float* %p, align 4
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%3 = insertelement <4 x float> %2, float %1, i32 1
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%4 = insertelement <4 x float> %3, float %1, i32 2
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%5 = insertelement <4 x float> %4, float %1, i32 3
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%6 = shufflevector <4 x float> %5, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %6
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}
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define <8 x float> @splat_concat2(float* %p) {
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; CHECK-LABEL: splat_concat2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vbroadcastss (%rdi), %ymm0
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; CHECK-NEXT: retq
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%1 = load float, float* %p, align 4
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%3 = insertelement <4 x float> %2, float %1, i32 1
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%4 = insertelement <4 x float> %3, float %1, i32 2
|
|
%5 = insertelement <4 x float> %4, float %1, i32 3
|
|
%6 = insertelement <4 x float> undef, float %1, i32 0
|
|
%7 = insertelement <4 x float> %6, float %1, i32 1
|
|
%8 = insertelement <4 x float> %7, float %1, i32 2
|
|
%9 = insertelement <4 x float> %8, float %1, i32 3
|
|
%10 = shufflevector <4 x float> %5, <4 x float> %9, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
ret <8 x float> %10
|
|
}
|
|
|
|
define <4 x double> @splat_concat3(double* %p) {
|
|
; CHECK-LABEL: splat_concat3:
|
|
; CHECK: ## BB#0:
|
|
; CHECK-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
; CHECK-NEXT: retq
|
|
%1 = load double, double* %p, align 8
|
|
%2 = insertelement <2 x double> undef, double %1, i32 0
|
|
%3 = insertelement <2 x double> %2, double %1, i32 1
|
|
%4 = shufflevector <2 x double> %3, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
|
|
ret <4 x double> %4
|
|
}
|
|
|
|
define <4 x double> @splat_concat4(double* %p) {
|
|
; CHECK-LABEL: splat_concat4:
|
|
; CHECK: ## BB#0:
|
|
; CHECK-NEXT: vbroadcastsd (%rdi), %ymm0
|
|
; CHECK-NEXT: retq
|
|
%1 = load double, double* %p, align 8
|
|
%2 = insertelement <2 x double> undef, double %1, i32 0
|
|
%3 = insertelement <2 x double> %2, double %1, i32 1
|
|
%4 = insertelement <2 x double> undef, double %1, i32 0
|
|
%5 = insertelement <2 x double> %2, double %1, i32 1
|
|
%6 = shufflevector <2 x double> %3, <2 x double> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
ret <4 x double> %6
|
|
}
|