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45d6ddee89
As discussed in D11886, this patch moves the SSE/AVX vector blend folding to instcombiner from PerformINTRINSIC_WO_CHAINCombine (which allows us to remove this completely). InstCombiner already had partial support for this, I just had to add support for zero (ConstantAggregateZero) masks and also the case where both selection inputs were the same (allowing us to ignore the mask). I also moved all the relevant combine tests into InstCombine/blend_x86.ll Differential Revision: http://reviews.llvm.org/D11934 llvm-svn: 244723
91 lines
2.6 KiB
LLVM
91 lines
2.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s
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; Verify that the backend correctly combines AVX2 builtin intrinsics.
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define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a0, i32 7)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a0, i32 7)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a0, i32 7)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <16 x i16> @test2_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 0)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test2_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 0)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test2_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 0)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <16 x i16> @test3_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 -1)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test3_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 -1)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 -1)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
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declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
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declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)
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