Christudasan Devadasan aa8030a6bf GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM ... It is good to have a combined `divrem` instruction when the `div` and `rem` are computed from identical input operands. Some targets can lower them through a single expansion that computes both division and remainder. It effectively reduces the number of instructions than individually expanding them. Reviewed By: arsenm, paquette Differential Revision: https://reviews.llvm.org/D96013		2021-03-10 18:46:07 +05:30
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GlobalISel	GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM	2021-03-10 18:46:07 +05:30
CGPassBuilderOption.h	[llvm] Fix header guards (NFC)	2021-02-05 21:02:06 -08:00
CodeGenCWrappers.h	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
GenericOpcodes.td	GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM	2021-03-10 18:46:07 +05:30
Target.td	[M68k][TableGen](1/8) TableGen related changes	2021-03-08 12:30:56 -08:00
TargetCallingConv.td	[TableGen] Clean up Target .td include files	2020-11-17 09:45:14 -05:00
TargetInstrPredicate.td	[TableGen] Clean up Target .td include files	2020-11-17 09:45:14 -05:00
TargetIntrinsicInfo.h	TargetIntrinsicInfo.h - remove unnecessary Compiler.h include. NFC.	2020-05-19 09:28:13 +01:00
TargetItinerary.td	[TableGen] Clean up Target .td include files	2020-11-17 09:45:14 -05:00
TargetLoweringObjectFile.h	Basic block sections should enable function sections implicitly.	2021-02-16 16:27:16 -08:00
TargetMachine.h	Add -fbinutils-version= to gate ELF features on the specified binutils version	2021-01-26 12:28:23 -08:00
TargetOptions.h	Add -fbinutils-version= to gate ELF features on the specified binutils version	2021-01-26 12:28:23 -08:00
TargetPfmCounters.td	[TableGen] Clean up Target .td include files	2020-11-17 09:45:14 -05:00
TargetSchedule.td	[MCA] Add support for in-order CPUs	2021-03-04 14:08:19 +03:00
TargetSelectionDAG.td	[IR] Introduce llvm.experimental.vector.splice intrinsic	2021-03-09 10:44:22 +00:00