mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-18 18:42:46 +02:00
ae65e281f3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
95 lines
3.9 KiB
TableGen
95 lines
3.9 KiB
TableGen
//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Define TII for use in SchedVariant Predicates.
|
|
// const MachineInstr *MI and const TargetSchedModel *SchedModel
|
|
// are defined by default.
|
|
def : PredicateProlog<[{
|
|
const AArch64InstrInfo *TII =
|
|
static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
|
|
(void)TII;
|
|
}]>;
|
|
|
|
// AArch64 Scheduler Definitions
|
|
|
|
def WriteImm : SchedWrite; // MOVN, MOVZ
|
|
// TODO: Provide variants for MOV32/64imm Pseudos that dynamically
|
|
// select the correct sequence of WriteImms.
|
|
|
|
def WriteI : SchedWrite; // ALU
|
|
def WriteISReg : SchedWrite; // ALU of Shifted-Reg
|
|
def WriteIEReg : SchedWrite; // ALU of Extended-Reg
|
|
def ReadI : SchedRead; // ALU
|
|
def ReadISReg : SchedRead; // ALU of Shifted-Reg
|
|
def ReadIEReg : SchedRead; // ALU of Extended-Reg
|
|
def WriteExtr : SchedWrite; // EXTR shifts a reg pair
|
|
def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
|
|
def WriteIS : SchedWrite; // Shift/Scale
|
|
def WriteID32 : SchedWrite; // 32-bit Divide
|
|
def WriteID64 : SchedWrite; // 64-bit Divide
|
|
def ReadID : SchedRead; // 32/64-bit Divide
|
|
def WriteIM32 : SchedWrite; // 32-bit Multiply
|
|
def WriteIM64 : SchedWrite; // 64-bit Multiply
|
|
def ReadIM : SchedRead; // 32/64-bit Multiply
|
|
def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
|
|
def WriteBr : SchedWrite; // Branch
|
|
def WriteBrReg : SchedWrite; // Indirect Branch
|
|
|
|
def WriteLD : SchedWrite; // Load from base addr plus immediate offset
|
|
def WriteST : SchedWrite; // Store to base addr plus immediate offset
|
|
def WriteSTP : SchedWrite; // Store a register pair.
|
|
def WriteAdr : SchedWrite; // Address pre/post increment.
|
|
|
|
def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
|
|
def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
|
|
def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
|
|
|
|
// Serialized two-level address load.
|
|
// EXAMPLE: LOADGot
|
|
def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
|
|
|
|
// Serialized two-level address lookup.
|
|
// EXAMPLE: MOVaddr...
|
|
def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;
|
|
|
|
// The second register of a load-pair.
|
|
// LDP,LDPSW,LDNP,LDXP,LDAXP
|
|
def WriteLDHi : SchedWrite;
|
|
|
|
// Store-exclusive is a store followed by a dependent load.
|
|
def WriteSTX : WriteSequence<[WriteST, WriteLD]>;
|
|
|
|
def WriteSys : SchedWrite; // Long, variable latency system ops.
|
|
def WriteBarrier : SchedWrite; // Memory barrier.
|
|
def WriteHint : SchedWrite; // Hint instruction.
|
|
|
|
def WriteF : SchedWrite; // General floating-point ops.
|
|
def WriteFCmp : SchedWrite; // Floating-point compare.
|
|
def WriteFCvt : SchedWrite; // Float conversion.
|
|
def WriteFCopy : SchedWrite; // Float-int register copy.
|
|
def WriteFImm : SchedWrite; // Floating-point immediate.
|
|
def WriteFMul : SchedWrite; // Floating-point multiply.
|
|
def WriteFDiv : SchedWrite; // Floating-point division.
|
|
|
|
def WriteV : SchedWrite; // Vector ops.
|
|
def WriteVLD : SchedWrite; // Vector loads.
|
|
def WriteVST : SchedWrite; // Vector stores.
|
|
|
|
def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP)
|
|
|
|
// Read the unwritten lanes of the VLD's destination registers.
|
|
def ReadVLD : SchedRead;
|
|
|
|
// Sequential vector load and shuffle.
|
|
def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>;
|
|
def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
|
|
|
|
// Store a shuffled vector.
|
|
def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
|
|
def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;
|