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53e0eee9de
Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. llvm-svn: 159409
74 lines
1.6 KiB
LLVM
74 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic -enable-pie \
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; RUN: | FileCheck -check-prefix=X32 %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic -enable-pie \
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; RUN: | FileCheck -check-prefix=X64 %s
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@i = thread_local global i32 15
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@i2 = external thread_local global i32
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define i32 @f1() {
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; X32: f1:
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; X32: movl %gs:i@NTPOFF, %eax
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; X32-NEXT: ret
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; X64: f1:
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; X64: movl %fs:i@TPOFF, %eax
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; X64-NEXT: ret
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entry:
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%tmp1 = load i32* @i
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ret i32 %tmp1
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}
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define i32* @f2() {
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; X32: f2:
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; X32: movl %gs:0, %eax
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; X32-NEXT: leal i@NTPOFF(%eax), %eax
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; X32-NEXT: ret
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; X64: f2:
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; X64: movq %fs:0, %rax
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; X64-NEXT: leaq i@TPOFF(%rax), %rax
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; X64-NEXT: ret
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entry:
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ret i32* @i
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}
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define i32 @f3() {
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; X32: f3:
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; X32: calll .L{{[0-9]+}}$pb
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; X32-NEXT: .L{{[0-9]+}}$pb:
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; X32-NEXT: popl %eax
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; X32-NEXT: .Ltmp{{[0-9]+}}:
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; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %eax
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; X32-NEXT: movl i2@GOTNTPOFF(%eax), %eax
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; X32-NEXT: movl %gs:(%eax), %eax
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; X32-NEXT: ret
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; X64: f3:
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; X64: movq i2@GOTTPOFF(%rip), %rax
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; X64-NEXT: movl %fs:(%rax), %eax
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; X64-NEXT: ret
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entry:
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%tmp1 = load i32* @i2
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ret i32 %tmp1
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}
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define i32* @f4() {
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; X32: f4:
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; X32: calll .L{{[0-9]+}}$pb
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; X32-NEXT: .L{{[0-9]+}}$pb:
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; X32-NEXT: popl %ecx
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; X32-NEXT: .Ltmp{{[0-9]+}}:
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; X32-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp{{[0-9]+}}-.L{{[0-9]+}}$pb), %ecx
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; X32-NEXT: movl %gs:0, %eax
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; X32-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
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; X32-NEXT: ret
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; X64: f4:
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; X64: movq %fs:0, %rax
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; X64-NEXT: addq i2@GOTTPOFF(%rip), %rax
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; X64-NEXT: ret
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entry:
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ret i32* @i2
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}
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