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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 05:23:45 +02:00
llvm-mirror/test/CodeGen
Quentin Colombet aaf2db6c80 [X86] Make sure we do not clobber RBX with cmpxchg when used as a base pointer.
cmpxchg[8|16]b uses RBX as one of its argument.
In other words, using this instruction clobbers RBX as it is defined to hold one
the input. When the backend uses dynamically allocated stack, RBX is used as a
reserved register for the base pointer. 

Reserved registers have special semantic that only the target understands and
enforces, because of that, the register allocator don’t use them, but also,
don’t try to make sure they are used properly (remember it does not know how
they are supposed to be used).

Therefore, when RBX is used as a reserved register but defined by something that
is not compatible with that use, the register allocator will not fix the
surrounding code to make sure it gets saved and restored properly around the
broken code. This is the responsibility of the target to do the right thing with
its reserved register.

To fix that, when the base pointer needs to be preserved, we use a different
pseudo instruction for cmpxchg that save rbx.
That pseudo takes two more arguments than the regular instruction:
- One is the value to be copied into RBX to set the proper value for the
  comparison.
- The other is the virtual register holding the save of the value of RBX as the
  base pointer. This saving is done as part of isel (i.e., we emit a copy from
  rbx).

cmpxchg_save_rbx <regular cmpxchg args>, input_for_rbx_reg, save_of_rbx_as_bp

This gets expanded into:
rbx = copy input_for_rbx_reg
cmpxchg <regular cmpxchg args>
rbx = save_of_rbx_as_bp

Note: The actual modeling of the pseudo is a bit more complicated to make sure
the interferes that appears after the pseudo gets expanded are properly modeled
before that expansion.

This fixes PR26883.

llvm-svn: 263325
2016-03-12 02:25:27 +00:00
..
AArch64 [AArch64] Don't blindly lower f16/f128 FCCMPs. 2016-03-11 22:02:58 +00:00
AMDGPU Update test case to appease bots after 263255. 2016-03-11 17:33:36 +00:00
ARM [ARM] Cortex-R8 support 2016-03-10 17:38:41 +00:00
BPF
CPP
Generic Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86. 2016-02-25 00:12:18 +00:00
Hexagon Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Inputs
Mips [mips] MIPSR6 Instruction itineraries 2016-03-11 13:05:06 +00:00
MIR [MIR] Teach the parser/printer that generic virtual registers do not need a register class. 2016-03-08 01:17:03 +00:00
MSP430 MSP430InstrInfo::loadRegFromStackSlot forgets to set register def. 2016-02-24 15:15:02 +00:00
NVPTX [NVPTX] Use different, convergent MIs for convergent calls. 2016-03-01 19:24:03 +00:00
PowerPC [PPC] backend changes to generate xvabs[s,d]p and xvnabs[s,d]p instructions 2016-03-09 17:48:01 +00:00
SPARC Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
SystemZ [SystemZ] Fix ABI for i128 argument and return types 2016-02-19 14:10:21 +00:00
Thumb Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Thumb2 ARM: Introduce conservative load/store optimization mode 2016-03-02 19:20:00 +00:00
WebAssembly [WebAssembly] Implement irreducible control flow. 2016-03-09 02:01:14 +00:00
WinEH [WinEH] Make setjmp work correctly with EH 2016-02-29 19:16:03 +00:00
X86 [X86] Make sure we do not clobber RBX with cmpxchg when used as a base pointer. 2016-03-12 02:25:27 +00:00
XCore [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00