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09e241eb0f
Summary: In this implementation, LiveIntervalAnalysis invents a few register masks on basic block boundaries that preserve no registers. The nice thing about this is that it prevents the prologue inserter from thinking it needs to spill all XMM CSRs, because it doesn't see any explicit physreg defs in the MI. Reviewers: MatzeB, qcolombet, JosephTremoulet, majnemer Subscribers: MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D14407 llvm-svn: 252318
144 lines
5.3 KiB
C++
144 lines
5.3 KiB
C++
//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
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#include "PPC.h"
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#include "llvm/ADT/DenseMap.h"
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#define GET_REGINFO_HEADER
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#include "PPCGenRegisterInfo.inc"
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namespace llvm {
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inline static unsigned getCRFromCRBit(unsigned SrcReg) {
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unsigned Reg = 0;
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if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
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SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
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Reg = PPC::CR0;
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else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
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SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
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Reg = PPC::CR1;
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else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
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SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
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Reg = PPC::CR2;
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else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
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SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
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Reg = PPC::CR3;
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else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
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SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
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Reg = PPC::CR4;
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else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
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SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
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Reg = PPC::CR5;
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else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
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SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
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Reg = PPC::CR6;
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else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
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SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
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Reg = PPC::CR7;
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assert(Reg != 0 && "Invalid CR bit register");
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return Reg;
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}
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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const PPCTargetMachine &TM;
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public:
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PPCRegisterInfo(const PPCTargetMachine &TM);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const override;
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const uint32_t *getNoPreservedMask() const override;
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void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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/// We require the register scavenger.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
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return true;
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}
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void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
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void lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRBitSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRBitRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerVRSAVERestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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// Support for virtual base registers.
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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// Base pointer (stack realignment) support.
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unsigned getBaseRegister(const MachineFunction &MF) const;
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bool hasBasePointer(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif
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