Tim Northover ab2c0f5890 AArch64: use 32-bit MOV rather than UBFX to truncate registers. ... It's potentially more efficient on Cyclone, and from the optimization guides & schedulers looks like it has no effect on Cortex-A53 or A57. In general you'd expect a MOV to be about the most efficient instruction with its semantics, even though the official "UXTW" alias is really a UBFX. llvm-svn: 243576		2015-07-29 21:34:32 +00:00
..
AArch64	AArch64: use 32-bit MOV rather than UBFX to truncate registers.	2015-07-29 21:34:32 +00:00
AMDGPU	AMDGPU: Don't try to use LDS/vector for private if pointer value stored	2015-07-28 18:47:00 +00:00
ARM	[ARM] Define subtarget feature strict-align.	2015-07-28 22:44:28 +00:00
BPF
CPP
Generic	Move unit tests to target specific directories.	2015-07-28 17:32:49 +00:00
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs
Mips	[mips][FastISel] Fix call lowering by bailing out on "fastcc" calls.	2015-07-28 21:43:31 +00:00
MIR	MIR Serialization: Serialize the frame info's save and restore points.	2015-07-29 21:09:09 +00:00
MSP430
NVPTX	Roll forward r242871	2015-07-29 18:59:09 +00:00
PowerPC	[PPC] Fix PR24216: Don't generate splat for misaligned shuffle mask	2015-07-29 14:31:57 +00:00
SPARC
SystemZ
Thumb	[ARM] Define subtarget feature strict-align.	2015-07-28 22:44:28 +00:00
Thumb2	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2	2015-07-21 00:18:59 +00:00
WebAssembly	WebAssembly: add a generic CPU	2015-07-27 23:25:54 +00:00
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	[X86][SSE] Vectorize i64 ASHR operations	2015-07-29 20:31:45 +00:00
XCore