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69 lines
1.9 KiB
LLVM
69 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s
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; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s
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define arm_aapcs_vfpcc float @test_vmov_f32() {
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; CHECK-LABEL: test_vmov_f32:
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; CHECK: vmov.f32 d0, #1.0
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; CHECK-NONEONFP: vmov.f32 s0, #1.0
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ret float 1.0
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}
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define arm_aapcs_vfpcc float @test_vmov_imm() {
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; CHECK-LABEL: test_vmov_imm:
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; CHECK: vmov.i32 d0, #0
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; CHECK-NONEON-LABEL: test_vmov_imm:
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; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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ret float 0.0
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}
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define arm_aapcs_vfpcc float @test_vmvn_imm() {
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; CHECK-LABEL: test_vmvn_imm:
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; CHECK: vmvn.i32 d0, #0xb0000000
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; CHECK-NONEON-LABEL: test_vmvn_imm:
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; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
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ret float 8589934080.0
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}
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define arm_aapcs_vfpcc double @test_vmov_f64() {
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; CHECK-LABEL: test_vmov_f64:
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; CHECK: vmov.f64 d0, #1.0
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; CHECK-NONEON-LABEL: test_vmov_f64:
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; CHECK-NONEON: vmov.f64 d0, #1.0
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ret double 1.0
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}
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define arm_aapcs_vfpcc double @test_vmov_double_imm() {
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; CHECK-LABEL: test_vmov_double_imm:
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; CHECK: vmov.i32 d0, #0
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; CHECK-NONEON-LABEL: test_vmov_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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ret double 0.0
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}
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define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
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; CHECK-LABEL: test_vmvn_double_imm:
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; CHECK: vmvn.i32 d0, #0xb0000000
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; CHECK-NONEON-LABEL: test_vmvn_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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ret double 0x4fffffff4fffffff
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}
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; Make sure we don't ignore the high half of 64-bit values when deciding whether
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; a vmov/vmvn is possible.
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define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
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; CHECK-LABEL: test_notvmvn_double_imm:
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; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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; CHECK-NONEON-LABEL: test_notvmvn_double_imm:
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; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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ret double 0x4fffffffffffffff
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}
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