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176 lines
4.3 KiB
LLVM
176 lines
4.3 KiB
LLVM
; Test 32-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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declare i32 @foo()
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; Check AR.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: ar %r2, %r3
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; CHECK: br %r14
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the low end of the A range.
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define i32 @f2(i32 %a, i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: a %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i32 *%src
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the high end of the aligned A range.
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define i32 @f3(i32 %a, i32 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: a %r2, 4092(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1023
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the next word up, which should use AY instead of A.
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define i32 @f4(i32 %a, i32 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: ay %r2, 4096(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 1024
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the high end of the aligned AY range.
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define i32 @f5(i32 %a, i32 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: ay %r2, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f6(i32 %a, i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, 524288
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; CHECK: a %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the high end of the negative aligned AY range.
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define i32 @f7(i32 %a, i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: ay %r2, -4(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the low end of the AY range.
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define i32 @f8(i32 %a, i32 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: ay %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f9(i32 %a, i32 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r3, -524292
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; CHECK: a %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check that A allows an index.
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define i32 @f10(i32 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4092
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check that AY allows an index.
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define i32 @f11(i32 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%add = add i32 %a, %b
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ret i32 %add
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}
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; Check that additions of spilled values can use A rather than AR.
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define i32 @f12(i32 *%ptr0) {
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; CHECK-LABEL: f12:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: a %r2, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32 *%ptr0, i64 18
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%val0 = load i32 *%ptr0
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%val1 = load i32 *%ptr1
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%val2 = load i32 *%ptr2
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%val3 = load i32 *%ptr3
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%val4 = load i32 *%ptr4
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%val5 = load i32 *%ptr5
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%val6 = load i32 *%ptr6
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%val7 = load i32 *%ptr7
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%val8 = load i32 *%ptr8
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%val9 = load i32 *%ptr9
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%ret = call i32 @foo()
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%add0 = add i32 %ret, %val0
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%add1 = add i32 %add0, %val1
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%add2 = add i32 %add1, %val2
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%add3 = add i32 %add2, %val3
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%add4 = add i32 %add3, %val4
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%add5 = add i32 %add4, %val5
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%add6 = add i32 %add5, %val6
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%add7 = add i32 %add6, %val7
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%add8 = add i32 %add7, %val8
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%add9 = add i32 %add8, %val9
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ret i32 %add9
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}
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