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https://github.com/RPCS3/llvm-mirror.git
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98ea718b1d
Summary: Fixes an issue where a test attempts to use -mcpu=x86-64 on non-X86-64 targets. This triggers an assertion in the MIPS backend since it doesn't know what ABI to use by default for unrecognized processors. CC: llvm-commits, rafael Differential Revision: http://llvm-reviews.chandlerc.com/D2877 llvm-svn: 202369
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc --march=x86 --mcpu=x86-64 --mattr=ssse3 < %s
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; RUN: llc --march=x86-64 --mcpu=x86-64 --mattr=ssse3 < %s
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;PR18045:
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;Issue of selection for 'v4i32 load'.
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;This instruction is not legal for X86 CPUs with sse < 'sse4.1'.
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;This node was generated by X86ISelLowering.cpp, EltsFromConsecutiveLoads
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;static function after legalize stage.
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@e = external global [4 x i32], align 4
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@f = external global [4 x i32], align 4
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; Function Attrs: nounwind
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define void @fn3(i32 %el) {
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entry:
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%0 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)
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%1 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 1)
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%2 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 2)
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%3 = load i32* getelementptr inbounds ([4 x i32]* @e, i32 0, i32 3)
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%4 = insertelement <4 x i32> undef, i32 %0, i32 0
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%5 = insertelement <4 x i32> %4, i32 %1, i32 1
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%6 = insertelement <4 x i32> %5, i32 %2, i32 2
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%7 = insertelement <4 x i32> %6, i32 %3, i32 3
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%8 = add <4 x i32> %6, %7
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store <4 x i32> %8, <4 x i32>* bitcast ([4 x i32]* @f to <4 x i32>*)
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ret void
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}
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