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If the return values can't be lowered to registers SelectionDAG performs the sret demotion. This patch contains the basic implementation for the same in the GlobalISel pipeline. Furthermore, targets should bring relevant changes during lowerFormalArguments, lowerReturn and lowerCall to make use of this feature. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D92953
52 lines
1.7 KiB
C++
52 lines
1.7 KiB
C++
//===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVCallLowering.h"
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#include "RISCVISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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using namespace llvm;
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RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
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: CallLowering(&TLI) {}
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bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI) const {
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MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
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if (Val != nullptr) {
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return false;
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}
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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if (F.arg_empty())
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return true;
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return false;
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}
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bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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return false;
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}
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