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699846f1a5
Changes TTI function getIntImmCostInst to take an additional Instruction parameter, which enables us to be able to check it is part of a min(max())/max(min()) pattern that will match SSAT. We can then mark the constant used as free to prevent it being hoisted so SSAT can still be generated. Required minor changes in some non-ARM backends to allow for the optional parameter to be included. Differential Revision: https://reviews.llvm.org/D87457
55 lines
2.1 KiB
C++
55 lines
2.1 KiB
C++
//===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines a TargetTransformInfo::Concept conforming object specific
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/// to the RISC-V target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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namespace llvm {
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class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
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using BaseT = BasicTTIImplBase<RISCVTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const RISCVSubtarget *ST;
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const RISCVTargetLowering *TLI;
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const RISCVSubtarget *getST() const { return ST; }
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const RISCVTargetLowering *getTLI() const { return TLI; }
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public:
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explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
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int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr);
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int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty, TTI::TargetCostKind CostKind);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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