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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
226 lines
7.7 KiB
C++
226 lines
7.7 KiB
C++
//===-- SnippetGenerator.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <array>
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#include <string>
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#include "Assembler.h"
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#include "MCInstrDescView.h"
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#include "SnippetGenerator.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "llvm/Support/Program.h"
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namespace llvm {
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namespace exegesis {
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std::vector<CodeTemplate> getSingleton(CodeTemplate &&CT) {
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std::vector<CodeTemplate> Result;
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Result.push_back(std::move(CT));
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return Result;
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}
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SnippetGeneratorFailure::SnippetGeneratorFailure(const llvm::Twine &S)
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: llvm::StringError(S, llvm::inconvertibleErrorCode()) {}
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SnippetGenerator::SnippetGenerator(const LLVMState &State) : State(State) {}
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SnippetGenerator::~SnippetGenerator() = default;
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llvm::Expected<std::vector<BenchmarkCode>>
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SnippetGenerator::generateConfigurations(const Instruction &Instr) const {
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if (auto E = generateCodeTemplates(Instr)) {
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const auto &RATC = State.getRATC();
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std::vector<BenchmarkCode> Output;
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for (CodeTemplate &CT : E.get()) {
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const llvm::BitVector &ForbiddenRegs =
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CT.ScratchSpacePointerInReg
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? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
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: RATC.emptyRegisters();
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// TODO: Generate as many BenchmarkCode as needed.
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{
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BenchmarkCode BC;
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BC.Info = CT.Info;
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for (InstructionTemplate &IT : CT.Instructions) {
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randomizeUnsetVariables(ForbiddenRegs, IT);
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BC.Instructions.push_back(IT.build());
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}
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if (CT.ScratchSpacePointerInReg)
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BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
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BC.RegisterInitialValues =
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computeRegisterInitialValues(CT.Instructions);
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Output.push_back(std::move(BC));
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}
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}
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return Output;
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} else
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return E.takeError();
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}
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std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
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const std::vector<InstructionTemplate> &Instructions) const {
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// Collect all register uses and create an assignment for each of them.
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// Ignore memory operands which are handled separately.
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// Loop invariant: DefinedRegs[i] is true iif it has been set at least once
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// before the current instruction.
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llvm::BitVector DefinedRegs = State.getRATC().emptyRegisters();
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std::vector<RegisterValue> RIV;
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for (const InstructionTemplate &IT : Instructions) {
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// Returns the register that this Operand sets or uses, or 0 if this is not
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// a register.
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const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {
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if (Op.isMemory())
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return 0;
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if (Op.isImplicitReg())
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return Op.getImplicitReg();
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if (Op.isExplicit() && IT.getValueFor(Op).isReg())
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return IT.getValueFor(Op).getReg();
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return 0;
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};
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// Collect used registers that have never been def'ed.
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for (const Operand &Op : IT.Instr.Operands) {
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if (Op.isUse()) {
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const unsigned Reg = GetOpReg(Op);
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if (Reg > 0 && !DefinedRegs.test(Reg)) {
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RIV.push_back(RegisterValue::zero(Reg));
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DefinedRegs.set(Reg);
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}
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}
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}
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// Mark defs as having been def'ed.
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for (const Operand &Op : IT.Instr.Operands) {
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if (Op.isDef()) {
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const unsigned Reg = GetOpReg(Op);
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if (Reg > 0)
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DefinedRegs.set(Reg);
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}
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}
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}
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return RIV;
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}
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llvm::Expected<std::vector<CodeTemplate>>
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generateSelfAliasingCodeTemplates(const Instruction &Instr) {
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const AliasingConfigurations SelfAliasing(Instr, Instr);
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if (SelfAliasing.empty())
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return llvm::make_error<SnippetGeneratorFailure>("empty self aliasing");
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std::vector<CodeTemplate> Result;
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Result.emplace_back();
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CodeTemplate &CT = Result.back();
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InstructionTemplate IT(Instr);
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if (SelfAliasing.hasImplicitAliasing()) {
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CT.Info = "implicit Self cycles, picking random values.";
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} else {
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CT.Info = "explicit self cycles, selecting one aliasing Conf.";
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// This is a self aliasing instruction so defs and uses are from the same
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// instance, hence twice IT in the following call.
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setRandomAliasing(SelfAliasing, IT, IT);
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}
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CT.Instructions.push_back(std::move(IT));
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return std::move(Result);
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}
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llvm::Expected<std::vector<CodeTemplate>>
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generateUnconstrainedCodeTemplates(const Instruction &Instr,
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llvm::StringRef Msg) {
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std::vector<CodeTemplate> Result;
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Result.emplace_back();
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CodeTemplate &CT = Result.back();
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CT.Info = llvm::formatv("{0}, repeating an unconstrained assignment", Msg);
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CT.Instructions.emplace_back(Instr);
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return std::move(Result);
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}
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std::mt19937 &randomGenerator() {
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static std::random_device RandomDevice;
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static std::mt19937 RandomGenerator(RandomDevice());
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return RandomGenerator;
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}
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static size_t randomIndex(size_t Size) {
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assert(Size > 0);
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std::uniform_int_distribution<> Distribution(0, Size - 1);
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return Distribution(randomGenerator());
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}
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template <typename C>
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static auto randomElement(const C &Container) -> decltype(Container[0]) {
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return Container[randomIndex(Container.size())];
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}
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static void randomize(const Instruction &Instr, const Variable &Var,
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llvm::MCOperand &AssignedValue,
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const llvm::BitVector &ForbiddenRegs) {
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const Operand &Op = Instr.getPrimaryOperand(Var);
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switch (Op.getExplicitOperandInfo().OperandType) {
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case llvm::MCOI::OperandType::OPERAND_IMMEDIATE:
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// FIXME: explore immediate values too.
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AssignedValue = llvm::MCOperand::createImm(1);
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break;
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case llvm::MCOI::OperandType::OPERAND_REGISTER: {
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assert(Op.isReg());
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auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
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assert(AllowedRegs.size() == ForbiddenRegs.size());
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for (auto I : ForbiddenRegs.set_bits())
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AllowedRegs.reset(I);
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AssignedValue = llvm::MCOperand::createReg(randomBit(AllowedRegs));
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break;
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}
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default:
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break;
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}
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}
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static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
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InstructionTemplate &IB) {
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assert(ROV.Op);
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if (ROV.Op->isExplicit()) {
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auto &AssignedValue = IB.getValueFor(*ROV.Op);
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if (AssignedValue.isValid()) {
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assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
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return;
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}
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AssignedValue = llvm::MCOperand::createReg(ROV.Reg);
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} else {
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assert(ROV.Op->isImplicitReg());
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assert(ROV.Reg == ROV.Op->getImplicitReg());
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}
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}
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size_t randomBit(const llvm::BitVector &Vector) {
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assert(Vector.any());
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auto Itr = Vector.set_bits_begin();
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for (size_t I = randomIndex(Vector.count()); I != 0; --I)
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++Itr;
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return *Itr;
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}
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void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
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InstructionTemplate &DefIB, InstructionTemplate &UseIB) {
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assert(!AliasingConfigurations.empty());
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assert(!AliasingConfigurations.hasImplicitAliasing());
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const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
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setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
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setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
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}
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void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
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InstructionTemplate &IT) {
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for (const Variable &Var : IT.Instr.Variables) {
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llvm::MCOperand &AssignedValue = IT.getValueFor(Var);
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if (!AssignedValue.isValid())
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randomize(IT.Instr, Var, AssignedValue, ForbiddenRegs);
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}
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}
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} // namespace exegesis
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} // namespace llvm
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