Kerry McLaughlin 44b117aaea [AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store ... Summary: The SVE masked load and store intrinsics introduced in D76688 rely on common llvm.masked.load/store nodes. This patch creates new ISD nodes for LD1(S) & ST1 to remove this dependency. Additionally, this adds support for sign & zero extending loads and truncating stores. Reviewers: sdesmalen, efriedma, cameron.mcinally, c-rhodes, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, andwar, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78204		2020-04-20 11:08:11 +01:00
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AArch64	[AArch64][SVE] Remove LD1/ST1 dependency on llvm.masked.load/store	2020-04-20 11:08:11 +01:00
AMDGPU	[AMDGPU] copyPhysReg() for 16 bit SGPR subregs	2020-04-17 11:59:39 -07:00
ARC
ARM	[ARM] Mir test for machine sinking multiple def instructions. NFC	2020-04-16 20:58:14 +01:00
AVR
BPF
Generic	[mir-strip-debug] Optionally preserve debug info that wasn't from debugify/mir-debugify	2020-04-10 15:24:14 -07:00
Hexagon	[Pipeliner] Fix the bug in pragma that disables the pipeliner.	2020-04-10 12:52:16 -05:00
Inputs
Lanai
Mips	[MIR] Add comments to INLINEASM immediate flag MachineOperands	2020-04-16 13:46:14 +02:00
MIR	[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef.	2020-04-17 21:55:44 -07:00
MSP430
NVPTX
PowerPC	[CodeGen] Support freeze expand for ppc_fp128	2020-04-20 07:27:41 +00:00
RISCV	[RISCV][AsmParser] Implement .option (no)pic	2020-04-17 12:08:30 +00:00
SPARC
SystemZ	[SystemZ] Bugfix in adjustSubwordCmp()	2020-04-15 12:58:39 +02:00
Thumb
Thumb2	[ARM][MVE] Add patterns for VRHADD	2020-04-20 10:05:21 +01:00
VE	[VE] Update integer arithmetic instructions	2020-04-15 09:47:51 +02:00
WebAssembly	[WebAssembly] Add int32 DW_OP_WASM_location variant	2020-04-16 16:32:17 -07:00
WinCFGuard
WinEH
X86	Handle CET for -exception-model sjlj	2020-04-20 11:13:40 +08:00
XCore