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2aa98cf3bd
For the program like below
struct key_t {
int pid;
char name[16];
};
extern void test1(char *);
int test() {
struct key_t key = {};
test1(key.name);
return 0;
}
For key.name, the llc/bpf may generate the below code:
R1 = R10 // R10 is the frame pointer
R1 += -24 // framepointer adjustment
R1 |= 4 // R1 is then used as the first parameter of test1
OR operation is not recognized by in-kernel verifier.
This patch introduces an intermediate FI_ri instruction and
generates the following code that can be properly verified:
R1 = R10
R1 += -20
Patch by Yonghong Song <yhs@plumgrid.com>
llvm-svn: 249371
104 lines
3.3 KiB
C++
104 lines
3.3 KiB
C++
//===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the BPF implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "BPFRegisterInfo.h"
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#include "BPFSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "BPFGenRegisterInfo.inc"
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using namespace llvm;
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BPFRegisterInfo::BPFRegisterInfo()
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: BPFGenRegisterInfo(BPF::R0) {}
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const MCPhysReg *
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BPFRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_SaveList;
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}
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BitVector BPFRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(BPF::R10); // R10 is read only frame pointer
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Reserved.set(BPF::R11); // R11 is pseudo stack pointer
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return Reserved;
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}
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void BPFRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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DebugLoc DL = MI.getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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unsigned FrameReg = getFrameRegister(MF);
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int FrameIndex = MI.getOperand(i).getIndex();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineBasicBlock &MBB = *MI.getParent();
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if (MI.getOpcode() == BPF::MOV_rr) {
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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unsigned reg = MI.getOperand(i - 1).getReg();
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BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
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.addReg(reg)
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.addImm(Offset);
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return;
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}
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(i + 1).getImm();
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if (!isInt<32>(Offset))
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llvm_unreachable("bug in frame offset");
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if (MI.getOpcode() == BPF::FI_ri) {
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// architecture does not really support FI_ri, replace it with
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// MOV_rr <target_reg>, frame_reg
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// ADD_ri <target_reg>, imm
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unsigned reg = MI.getOperand(i - 1).getReg();
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BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
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.addReg(FrameReg);
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BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
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.addReg(reg)
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.addImm(Offset);
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// Remove FI_ri instruction
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MI.eraseFromParent();
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} else {
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i + 1).ChangeToImmediate(Offset);
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}
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}
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unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return BPF::R10;
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}
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