Bruno Cardoso Lopes ac0984dc7e Make this kind of lowering to be supported by 256-bit instructions: ... shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> To: shuffle (vload ptr)), undef, <1, 1, 1, 1> Fix PR10494 llvm-svn: 136691		2011-08-02 16:06:18 +00:00
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Alpha
ARM	Add support for the 'Q' constraint.	2011-07-29 21:18:58 +00:00
Blackfin	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CBackend	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CellSPU
CPP
Generic	Comment correction.	2011-07-12 03:39:22 +00:00
MBlaze
Mips	Lower memory barriers to sync instructions.	2011-07-19 23:30:50 +00:00
MSP430
PowerPC	Add MCObjectFileInfo and sink the MCSections initialization code from	2011-07-20 05:58:47 +00:00
PTX	PTX: corrected tests that were failing	2011-06-25 19:41:17 +00:00
SPARC
SystemZ
Thumb	Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.	2011-07-07 03:55:05 +00:00
Thumb2	Introduce MCCodeGenInfo, which keeps information that can affect codegen	2011-07-19 06:37:02 +00:00
X86	Make this kind of lowering to be supported by 256-bit instructions:	2011-08-02 16:06:18 +00:00
XCore	Fix crash with varargs function with no named parameters.	2011-08-01 16:45:59 +00:00