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https://github.com/RPCS3/llvm-mirror.git
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0a8fb0b4d7
I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32) isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if the assertzexti32 has an additional user. If we add a one use check it would just cause a fcvt.lu followed by a sext.w when only need a fcvt.wu to satisfy both users. To mitigate this I've added custom isel and new ISD opcodes for fcvt.wu. This allows us to keep know it started life as a conversion to i32 without needing to match multiple nodes. ComputeNumSignBits has been taught that this new nodes produces 33 sign bits. To prevent regressions when we need to zero extend the result of an (i32 (fptoui X)), I've added a DAG combine to convert it to an (i64 (fptoui X)) before type legalization. In most cases this would happen in InstCombine, but a zero_extend can be created for function returns or arguments. To keep everything consistent I've added new nodes for fptosi as well. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D106346
424 lines
18 KiB
TableGen
424 lines
18 KiB
TableGen
//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'F',
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// Single-Precision Floating-Point instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVFMV_W_X_RV64
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: SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
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def SDT_RISCVFMV_X_ANYEXTW_RV64
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: SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
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def STD_RISCVFCVT_W_RV64
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: SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisFP<1>]>;
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def riscv_fmv_w_x_rv64
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: SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>;
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def riscv_fmv_x_anyextw_rv64
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: SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>;
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def riscv_fcvt_w_rv64
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: SDNode<"RISCVISD::FCVT_W_RV64", STD_RISCVFCVT_W_RV64>;
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def riscv_fcvt_wu_rv64
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: SDNode<"RISCVISD::FCVT_WU_RV64", STD_RISCVFCVT_W_RV64>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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// Floating-point rounding mode
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def FRMArg : AsmOperandClass {
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let Name = "FRMArg";
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let RenderMethod = "addFRMArgOperands";
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let DiagnosticType = "InvalidFRMArg";
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}
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def frmarg : Operand<XLenVT> {
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let ParserMatchClass = FRMArg;
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let PrintMethod = "printFRMArg";
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let DecoderMethod = "decodeFRMArg";
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}
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr>
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: RVInstR4Frm<0b00, opcode, (outs FPR32:$rd),
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(ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
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opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
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class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
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(Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
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(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUS_rr_frm<bits<7> funct7, string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd),
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(ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr,
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"$rd, $rs1, $rs2, $funct3">;
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class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
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(Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
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RegisterClass rs1ty, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
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opcodestr, "$rd, $rs1">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty,
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string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
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(ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
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"$rd, $rs1, $funct3">;
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class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr,
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RegisterClass rdty, RegisterClass rs1ty>
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: InstAlias<OpcodeStr#" $rd, $rs1",
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(Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPCmpS_rr<bits<3> funct3, string opcodestr>
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: RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd),
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(ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">,
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Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtF] in {
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
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(ins GPR:$rs1, simm12:$imm12),
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"flw", "$rd, ${imm12}(${rs1})">,
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Sched<[WriteFLD32, ReadFMemBase]>;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
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(ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
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"fsw", "$rs2, ${imm12}(${rs1})">,
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Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>;
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def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">,
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Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
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def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">;
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def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">,
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Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
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def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">;
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def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">,
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Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
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def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">;
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def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">,
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Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
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def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">;
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def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
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Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
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def : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
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def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
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Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
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def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
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def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
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Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
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def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
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def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
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Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
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def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
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def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
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Sched<[WriteFSqrt32, ReadFSqrt32]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
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def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">,
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Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
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def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">,
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Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
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def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">,
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Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>;
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def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">,
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Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
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def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">,
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Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>;
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def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">,
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Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
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def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">,
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Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
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def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">,
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Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> {
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let rs2 = 0b00000;
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}
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def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
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def FLT_S : FPCmpS_rr<0b001, "flt.s">;
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def FLE_S : FPCmpS_rr<0b000, "fle.s">;
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def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">,
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Sched<[WriteFClass32, ReadFClass32]> {
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let rs2 = 0b00000;
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}
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def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">,
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Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>;
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def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">,
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Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>;
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def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">,
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Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> {
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let rs2 = 0b00000;
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}
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} // Predicates = [HasStdExtF]
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let Predicates = [HasStdExtF, IsRV64] in {
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def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">,
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Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>;
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def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">,
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Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>;
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def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">,
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Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>;
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def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">,
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Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
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} // Predicates = [HasStdExtF, IsRV64]
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtF] in {
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def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
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def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
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def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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// fgt.s/fge.s are recognised by the GNU assembler but the canonical
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// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
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def : InstAlias<"fgt.s $rd, $rs, $rt",
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(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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def : InstAlias<"fge.s $rd, $rs, $rt",
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(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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// The following csr instructions actually alias instructions from the base ISA.
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// However, it only makes sense to support them when the F extension is enabled.
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// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
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def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
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def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
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def : InstAlias<"fscsr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 2>;
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// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them
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// zero weight.
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def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>;
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def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
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def : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>;
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def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>;
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def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
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def : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>;
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def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>;
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def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>;
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def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>;
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def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>;
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def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
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def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
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def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
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// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
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// spellings should be supported by standard tools.
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def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
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def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
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def PseudoFLW : PseudoFloatLoad<"flw", FPR32>;
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def PseudoFSW : PseudoStore<"fsw", FPR32>;
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} // Predicates = [HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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/// Floating point constants
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def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
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/// Generic pattern classes
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class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
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class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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: Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
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let Predicates = [HasStdExtF] in {
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/// Float constants
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def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
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/// Float conversion operations
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// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
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// are defined later.
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/// Float arithmetic operations
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def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
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def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
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def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
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def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
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def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
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def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
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def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
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def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
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def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
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// fmadd: rs1 * rs2 + rs3
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def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
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(FMADD_S $rs1, $rs2, $rs3, 0b111)>;
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// fmsub: rs1 * rs2 - rs3
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def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
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(FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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// fnmsub: -rs1 * rs2 + rs3
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def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
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(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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// fnmadd: -rs1 * rs2 - rs3
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def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
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(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
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// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
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// LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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def : PatFpr32Fpr32<fminnum, FMIN_S>;
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def : PatFpr32Fpr32<fmaxnum, FMAX_S>;
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/// Setcc
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def : PatFpr32Fpr32<seteq, FEQ_S>;
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def : PatFpr32Fpr32<setoeq, FEQ_S>;
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def : PatFpr32Fpr32<setlt, FLT_S>;
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def : PatFpr32Fpr32<setolt, FLT_S>;
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def : PatFpr32Fpr32<setle, FLE_S>;
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def : PatFpr32Fpr32<setole, FLE_S>;
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def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
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/// Loads
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defm : LdPat<load, FLW, f32>;
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/// Stores
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defm : StPat<store, FSW, FPR32, f32>;
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} // Predicates = [HasStdExtF]
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let Predicates = [HasStdExtF, IsRV32] in {
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// Moves (no conversion)
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def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
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def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>;
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// float->[u]int. Round-to-zero must be used.
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def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>;
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def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>;
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// float->int32 with current rounding mode.
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def : Pat<(i32 (lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>;
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// float->int32 rounded to nearest with ties rounded away from zero.
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def : Pat<(i32 (lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>;
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// [u]int->float. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
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} // Predicates = [HasStdExtF, IsRV32]
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let Predicates = [HasStdExtF, IsRV64] in {
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// Moves (no conversion)
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def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
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def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
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def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
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(FMV_X_W FPR32:$src)>;
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// Use target specific isd nodes to help us remember the result is sign
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// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
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// duplicated if it has another user that didn't need the sign_extend.
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def : Pat<(riscv_fcvt_w_rv64 FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
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def : Pat<(riscv_fcvt_wu_rv64 FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
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// float->[u]int64. Round-to-zero must be used.
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def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>;
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def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>;
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// float->int64 with current rounding mode.
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def : Pat<(i64 (lrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>;
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def : Pat<(i64 (llrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>;
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// float->int64 rounded to neartest with ties rounded away from zero.
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def : Pat<(i64 (lround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>;
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def : Pat<(i64 (llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>;
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// [u]int->fp. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>;
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def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>;
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} // Predicates = [HasStdExtF, IsRV64]
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