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llvm-mirror/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

29 lines
865 B
LLVM

; RUN: llc -mcpu=cyclone < %s | FileCheck %s
target datalayout = "e-i64:64-n32:64-S128"
target triple = "arm64-apple-ios"
%"struct.SU" = type { i32, %"struct.SU"*, i32*, i32, i32, %"struct.BO", i32, [5 x i8] }
%"struct.BO" = type { %"struct.RE" }
%"struct.RE" = type { i32, i32, i32, i32 }
; This is a read-modify-write of some bifields combined into an i48. It gets
; legalized into i32 and i16 accesses. Only a single store of zero to the low
; i32 part should be live.
; CHECK-LABEL: test:
; CHECK-NOT: ldr
; CHECK: str wzr
; CHECK-NOT: str
define void @test(%"struct.SU"* nocapture %su) {
entry:
%r1 = getelementptr inbounds %"struct.SU", %"struct.SU"* %su, i64 1, i32 5
%r2 = bitcast %"struct.BO"* %r1 to i48*
%r3 = load i48, i48* %r2, align 8
%r4 = and i48 %r3, -4294967296
%r5 = or i48 0, %r4
store i48 %r5, i48* %r2, align 8
ret void
}