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https://github.com/RPCS3/llvm-mirror.git
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916d7d74d3
This patch adds a bunch of CHECK lines to guard against implicit conversions of TypeSize -> uint64_t occuring in code-paths that previously were safe for scalable vectors.
69 lines
3.3 KiB
LLVM
69 lines
3.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; STNT1H, STNT1W, STNT1D: base + 64-bit index
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; e.g.
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; lsl z1.d, z1.d, #1
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; stnt1h { z0.d }, p0, [z0.d, x0]
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;
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define void @sstnt1h_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sstnt1h_index
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; CHECK: lsl z1.d, z1.d, #1
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; CHECK-NEXT: stnt1h { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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i16* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sstnt1w_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sstnt1w_index
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; CHECK: lsl z1.d, z1.d, #2
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; CHECK-NEXT: stnt1w { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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i32* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sstnt1d_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sstnt1d_index
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; CHECK: lsl z1.d, z1.d, #3
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; CHECK-NEXT: stnt1d { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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i64* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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define void @sstnt1d_index_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i64> %offsets) {
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; CHECK-LABEL: sstnt1d_index_double
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; CHECK: lsl z1.d, z1.d, #3
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; CHECK-NEXT: stnt1d { z0.d }, p0, [z1.d, x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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double* %base,
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<vscale x 2 x i64> %offsets)
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ret void
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}
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declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i64>)
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declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i64>)
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