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b227d8b168
Summary: For bitfield insert OR matching, check both operands for larger pattern first before checking for smaller pattern. Add pattern for unsigned bitfield insert-in-zero done with SHL+AND. Resolves PR21631. Reviewers: jmolloy, t.p.northover Subscribers: aemerson, rengolin, llvm-commits, mcrosier Differential Revision: http://reviews.llvm.org/D12908 llvm-svn: 248006
64 lines
1.4 KiB
LLVM
64 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
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define i64 @sbfiz64(i64 %v) {
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; CHECK-LABEL: sbfiz64:
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; CHECK: sbfiz x0, x0, #1, #16
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%shl = shl i64 %v, 48
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%shr = ashr i64 %shl, 47
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ret i64 %shr
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}
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define i32 @sbfiz32(i32 %v) {
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; CHECK-LABEL: sbfiz32:
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; CHECK: sbfiz w0, w0, #1, #14
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%shl = shl i32 %v, 18
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%shr = ashr i32 %shl, 17
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ret i32 %shr
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}
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define i64 @ubfiz64(i64 %v) {
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; CHECK-LABEL: ubfiz64:
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; CHECK: ubfiz x0, x0, #36, #11
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%shl = shl i64 %v, 53
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%shr = lshr i64 %shl, 17
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ret i64 %shr
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}
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define i32 @ubfiz32(i32 %v) {
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; CHECK-LABEL: ubfiz32:
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; CHECK: ubfiz w0, w0, #6, #24
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%shl = shl i32 %v, 8
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%shr = lshr i32 %shl, 2
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ret i32 %shr
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}
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define i64 @ubfiz64and(i64 %v) {
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; CHECK-LABEL: ubfiz64and:
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; CHECK: ubfiz x0, x0, #36, #11
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%shl = shl i64 %v, 36
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%and = and i64 %shl, 140668768878592
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ret i64 %and
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}
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define i32 @ubfiz32and(i32 %v) {
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; CHECK-LABEL: ubfiz32and:
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; CHECK: ubfiz w0, w0, #6, #24
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%shl = shl i32 %v, 6
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%and = and i32 %shl, 1073741760
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ret i32 %and
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}
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; Check that we don't generate a ubfiz if the lsl has more than one
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; use, since we'd just be replacing an and with a ubfiz.
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define i32 @noubfiz32(i32 %v) {
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; CHECK-LABEL: noubfiz32:
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; CHECK: lsl w[[REG1:[0-9]+]], w0, #6
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; CHECK: and w[[REG2:[0-9]+]], w[[REG1]], #0x3fffffc0
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; CHECK: add w0, w[[REG1]], w[[REG2]]
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; CHECK: ret
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%shl = shl i32 %v, 6
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%and = and i32 %shl, 1073741760
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%add = add i32 %shl, %and
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ret i32 %add
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}
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