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bc658bf60a
This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
19 lines
421 B
LLVM
19 lines
421 B
LLVM
; Test the Test Data Class instruction on z14
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare i32 @llvm.s390.tdc.f128(fp128, i64)
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; Check using as i32 - f128
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define i32 @f3(fp128 %x) {
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; CHECK-LABEL: f3
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; CHECK: vl %v0, 0(%r2)
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; CHECK: vrepg %v2, %v0, 1
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; CHECK: tcxb %f0, 123
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; CHECK: ipm %r2
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; CHECK: srl %r2, 28
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%res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123)
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ret i32 %res
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}
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