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On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. However, the default register class for 32-bit integers is GRX32, which also contains the high 32-bit part registers. In order to never end up with a case of such a COPY into a high reg, this patch adds a new simple pre-RA pass that selects such COPYs into target instructions. This pass also handles COPYs from CC (Condition Code register), and COPYs to CC can now also be emitted from a high reg in copyPhysReg(). Fixes: https://bugs.llvm.org/show_bug.cgi?id=44254 Review: Ulrich Weigand. Differential Revision: https://reviews.llvm.org/D75014
25 lines
746 B
LLVM
25 lines
746 B
LLVM
; RUN: llc < %s -mcpu=z196 -mtriple=s390x-linux-gnu -O0 \
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; RUN: -stop-before=regallocfast 2>&1 | FileCheck %s
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; RUN: llc < %s -mcpu=z196 -mtriple=s390x-linux-gnu -O3 \
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; RUN: -stop-before=livevars 2>&1 | FileCheck %s
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;
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; Test that copies to/from access registers are handled before regalloc with
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; GR32 regs.
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@x = dso_local thread_local global i32 0, align 4
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define weak_odr hidden i32* @fun0() {
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; CHECK: name: fun0
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; CHECK: {{%[0-9]+}}:gr32bit = EAR $a0
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; CHECK: {{%[0-9]+}}:gr32bit = EAR $a1
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ret i32* @x
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}
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define i32 @fun1() {
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; CHECK: name: fun1
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; CHECK: [[VREG0:%[0-9]+]]:gr32bit = COPY %0
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; CHECK-NEXT: $a1 = SAR [[VREG0]]
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; CHECK: {{%[0-9]+}}:gr32bit = EAR $a0
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%val = call i32 asm "blah", "={a0}, {a1}" (i32 0)
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ret i32 %val
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}
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