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b5b6e8e953
This adds support for constrained floating-point comparison intrinsics.
Specifically, we add:
declare <ty2>
@llvm.experimental.constrained.fcmp(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
declare <ty2>
@llvm.experimental.constrained.fcmps(<type> <op1>, <type> <op2>,
metadata <condition code>,
metadata <exception behavior>)
The first variant implements an IEEE "quiet" comparison (i.e. we only
get an invalid FP exception if either argument is a SNaN), while the
second variant implements an IEEE "signaling" comparison (i.e. we get
an invalid FP exception if either argument is any NaN).
The condition code is implemented as a metadata string. The same set
of predicates as for the fcmp instruction is supported (except for the
"true" and "false" predicates).
These new intrinsics are mapped by SelectionDAG codegen onto two new
ISD opcodes, ISD::STRICT_FSETCC and ISD::STRICT_FSETCCS, again
representing quiet vs. signaling comparison operations. Otherwise
those nodes look like SETCC nodes, with an additional chain argument
and result as usual for strict FP nodes. The patch includes support
for the common legalization operations for those nodes.
The patch also includes full SystemZ back-end support for the new
ISD nodes, mapping them to all available SystemZ instruction to
fully implement strict semantics (scalar and vector).
Differential Revision: https://reviews.llvm.org/D69281
57 lines
2.2 KiB
LLVM
57 lines
2.2 KiB
LLVM
; Test signaling vector floating-point comparisons on z13.
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; Note that these must be scalarized as we do not have native instructions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test v4f32.
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define <4 x i32> @f1(<4 x float> %val1, <4 x float> %val2) #0 {
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; CHECK-LABEL: f1:
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; CHECK: kebr
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; CHECK: kebr
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; CHECK: kebr
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; CHECK: kebr
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; CHECK: br %r14
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%cmp = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
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<4 x float> %val1, <4 x float> %val2,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test v2f64.
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define <2 x i64> @f2(<2 x i64> %dummy, <2 x double> %val1, <2 x double> %val2) #0 {
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; CHECK-LABEL: f2:
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; CHECK: {{kdbr|wfkdb}}
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; CHECK: {{kdbr|wfkdb}}
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; CHECK: br %r14
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%cmp = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
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<2 x double> %val1, <2 x double> %val2,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%ret = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test an f64 comparison that uses vector registers.
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define i64 @f3(i64 %a, i64 %b, double %f1, <2 x double> %vec) #0 {
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; CHECK-LABEL: f3:
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; CHECK: wfkdb %f0, %v24
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; CHECK-NEXT: locgrne %r2, %r3
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; CHECK: br %r14
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%f2 = extractelement <2 x double> %vec, i32 0
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%cond = call i1 @llvm.experimental.constrained.fcmps.f64(
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double %f1, double %f2,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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attributes #0 = { strictfp }
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declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float>, <4 x float>, metadata, metadata)
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declare <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double>, <2 x double>, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
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