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llvm-mirror/test/CodeGen
David Sherwood ac8a8b4ad9 [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorStores
In DAGTypeLegalizer::GenWidenVectorStores the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the main loop in
that function to use TypeSize instead of unsigned for tracking the
remaining store amount and offset increment. In addition, I've changed
the loop to use the new IncrementPointer helper function for updating
the addresses in each iteration, since this handles scalable vector
types.

Whilst fixing this function I also fixed a minor issue in
IncrementPointer whereby we were not adding the no-unsigned-wrap flag
for the add instruction in the same way as the fixed width case does.

Also, I've added a report_fatal_error in GenWidenVectorTruncStores,
since this code currently uses a sequence of element-by-element scalar
stores.

I've added new tests in

  CodeGen/AArch64/sve-intrinsics-stores.ll
  CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

for the changes in GenWidenVectorStores.

Differential Revision: https://reviews.llvm.org/D84937
2020-08-13 11:07:17 +01:00
..
AArch64 [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorStores 2020-08-13 11:07:17 +01:00
AMDGPU [AMDGPU] Pre-commit test for D85872 2020-08-13 13:07:27 +09:00
ARC
ARM [ARM] Unrestrict Armv8-a IT when at minsize 2020-08-10 14:59:53 +01:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC [NFC] [PowerPC] Rename SPE strict conversion test 2020-08-13 15:02:07 +08:00
RISCV
SPARC
SystemZ
Thumb
Thumb2 [ARM] Predicated VFMA patterns 2020-08-12 18:35:01 +01:00
VE [VE] Change to promote i32 AND/OR/XOR operations 2020-08-12 16:23:50 +09:00
WebAssembly [WebAssembly] Fix FastISel address calculation bug 2020-08-08 15:23:11 -07:00
WinCFGuard
WinEH
X86 [X86][GlobalISel] Legalize G_ICMP results to s8. 2020-08-12 10:13:59 -07:00
XCore